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ORCIDNalesh S 0001
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- affiliation: Cochin University of Science and Technology, Department of Electronics, India
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Journal Articles
- 2023
[j7]M. A. Muneeb, Nalesh S, S. Kala:
A physically unclonable function architecture with multiple responses on FPGA. Int. J. Embed. Syst. 16(1): 67-74 (2023)- 2019
- [j6]S. Kala
, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme. IET Comput. Digit. Tech. 13(2): 78-86 (2019) - [j5]S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2816-2828 (2019) - 2018
- [j4]Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy:
A Hardware Architecture for Radial Basis Function Neural Network Classifier. IEEE Trans. Parallel Distributed Syst. 29(3): 481-495 (2018) - 2017
- [j3]Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. 58: 320-328 (2017) - 2015
- [j2]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11(3): 426-435 (2015) - 2014
- [j1]Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan:
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60(7): 592-614 (2014)
Conference and Workshop Papers
- 2023
- [c19]Noble G, Nalesh S, S. Kala:
Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA. APCCAS 2023: 65-69 - [c18]Abhinav Kalvacherla, Rachana George, Nalesh S, S. Kala:
Approximate CNN on FPGA Using Toom-Cook Multiplier. iSES 2023: 271-276 - [c17]Noble G, Nalesh S, S. Kala:
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. VLSID 2023: 264-269 - 2022
- [c16]Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, S. Kala:
Adiabatic Physical Unclonable Function Using Cross-Coupled Pair. iSES 2022: 278-282 - 2021
- [c15]S. Sreeparvathy, Rachana George, Rose Mary Kuruvithadam, Nalesh S:
Fast Booth Multipliers Using Approximate 4: 2 Compressors. iSES 2021: 157-160 - [c14]Mahesh M, Nalesh S, S. Kala:
Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. SoCC 2021: 7-12 - [c13]Abi K. Krishnan, M. H. Supriya, Nalesh Sivanandan:
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA. VDAT 2021: 1-6 - [c12]Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala:
Hardware Acceleration of SpMV Multiplier for Deep Learning. VDAT 2021: 1-6 - 2019
- [c11]S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
Efficient Hardware Acceleration of Convolutional Neural Networks. SoCC 2019: 191-192 - [c10]S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. VLSID 2019: 209-214 - 2018
- [c9]S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi:
Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. DTIS 2018: 1-2 - [c8]S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan:
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. ISED 2018: 21-25 - 2016
- [c7]Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan:
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. VLSID 2016: 601-602 - 2015
- [c6]Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS 2015: 405-410 - [c5]Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS 2015: 7-12 - [c4]Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSID 2015: 153-158 - 2014
- [c3]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED 2014: 20-24 - [c2]Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS 2014: 215-224 - 2013
- [c1]S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan:
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS 2013: 3034-3037
Coauthor Index
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