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ORCIDJie Shen 0010
Person information
- affiliation: Rambus Inc., Sunnyvale, CA, USA
- affiliation (Phd 1998): Tsinghua University, Beijing, China
Other persons with the same name
- Jie Shen — disambiguation page
- Jie Shen 0001
![[0000-0002-4885-5732]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-4885-5732")
— Purdue University, Department of Mathematics, West Lafayette, IN, USA (and 2 more) - Jie Shen 0003 — National University of Defense Technology, College of Computer, Changsha, China (and 1 more)
- Jie Shen 0004 — Hohai University, College of Computer and Information, Nanjing, China
- Jie Shen 0005 — Stevens Institute of Technology, Hoboken, NJ, USA (and 2 more)
- Jie Shen 0006 — East China University of Science and Technology, School of Pharmacy, Shanghai, China
- Jie Shen 0007 — Liaoning Normal University, School of Mathematics, Dalian, China
- Jie Shen 0008 — Imperial College London, UK
- Jie Shen 0009 — University of Michigan-Dearborn, USA
- Jie Shen 0011 — Zhejiang University, Hangzhou, China
- Jie Shen 0012 — Shanghai Jiaotong University, China
- Jie Shen 0013 — University of Electronic Science and Technology of China, Chengdu, China
- Jie Shen 0014 — Zhejiang University of Technology, Institute of Cyberspace Security, College of Information Engineering, Hangzhou, China
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2010 – 2019
- 2012
[j3]Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. IEEE J. Solid State Circuits 47(4): 911-925 (2012)- [j2]Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. IEEE J. Solid State Circuits 47(4): 926-937 (2012) - 2010
- [c2]Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner, Ken Chang:
Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC 2010: 176-177
2000 – 2009
- 2009
- [j1]Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi:
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44(4): 1235-1247 (2009) - 2008
- [c1]Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang:
Clocking circuits for a 16Gb/s memory interface. CICC 2008: 435-438
Coauthor Index
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