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Jian Luo 0004

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affiliation: University of Electronic Science and Technology of China, The State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu, China

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Journal Articles

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2020
[j5]
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  - journals/tcas/LuoLLNWLY20
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  - https://dblp.org/rec/journals/tcas/LuoLLNWLY20
Jian Luo, Yang Liu, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Qi Yu:
A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1136-1148 (2020)
2019
[j4]
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Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu:
A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters. J. Circuits Syst. Comput. 28(6): 1950090:1-1950090:15 (2019)
[j3]
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Jing Li, Xin Ye, Jian Luo, Ning Ning, Qi Yu:
A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs. J. Circuits Syst. Comput. 28(6): 1950092:1-1950092:14 (2019)
2018
[j2]
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Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu:
The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction. IEEE Access 6: 7037-7043 (2018)
[j1]
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Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu:
A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1980-1988 (2018)

Conference and Workshop Papers

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2019
[c2]
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Jian Luo, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Yang Liu, Qi Yu:
A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC. ISCAS 2019: 1-5
2018
[c1]
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Jing Li, Jian Luo, Yongfeng Ding, Ning Ning:
A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter. APCCAS 2018: 86-89

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