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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 26
Volume 26, Number 1, January 2018
- Aatreyi Bal, Shamik Saha, Sanghamitra Roy
, Koushik Chakraborty:
Dynamic Choke Sensing for Timing Error Resilience in NTC Systems. 1-10 - Laura Rozo, Aaron Myles Landwehr, Yan Zheng, Chengmo Yang, Guang Gao:
Reliability-Aware Runtime Adaption Through a Statically Generated Task Schedule. 11-22 - Muayad J. Aljafar, Marek A. Perkowski, John M. Acken, Robin Tan:
A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures. 23-36 - Jongho Kim, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung-Hwan Choi:
Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation. 37-49 - Ing-Chao Lin, Yun Kae Law, Yuan Xie:
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. 50-62 - Maria Malik, Rajiv V. Joshi, Rouwaida Kanj, Shupeng Sun, Houman Homayoun, Tong Li:
Sparse Regression Driven Mixture Importance Sampling for Memory Design. 63-72 - Yuntao Liu, Yang Xie, Chongxi Bao, Ankur Srivastava:
A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions. 73-81 - Itamar Levi, Alexander Fish, Osnat Keren:
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information. 82-95 - Adwaya Kulkarni, Adam Page, Nasrin Attaran, Ali Jafari, Maria Malik, Houman Homayoun, Tinoosh Mohsenin:
An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications. 96-109 - Tosiron Adegbija, Ann Gordon-Ross:
PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking. 110-121 - Yujin Park, Junghee Yun, Dongchul Park, Sangwoo Kim, Suhwan Kim:
An Uncooled Microbolometer Infrared Imager With a Shutter-Based Successive-Approximation Calibration Loop. 122-132 - Jubin Mitra, Tapan Kumar Nayak:
An FPGA-Based Phase Measurement System. 133-142 - Xing Wang, Derek Chi-Wai Pao:
Memory-Based Architecture for Multicharacter Aho-Corasick String Matching. 143-154 - Xunzhao Yin, Behnam Sedighi, Melinda Varga, Mária Ercsey-Ravasz, Zoltán Toroczkai, Xiaobo Sharon Hu:
Efficient Analog Circuits for Boolean Satisfiability. 155-167 - Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha:
HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs. 168-181 - Ioannis Tsatsaragkos, Vassilis Paliouras:
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. 182-195 - Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang:
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. 196-200 - Yang Liu, Chenchang Zhan, Lidan Wang:
An Ultralow Power Subthreshold CMOS Voltage Reference Without Requiring Resistors or BJTs. 201-205 - Donghyun Kim, Hayoung Lee, Sungho Kang:
An Area-Efficient BIRA With 1-D Spare Segments. 206-210 - Zhen Gao, Qingqing Jing, Yumeng Li, Pedro Reviriego, Juan Antonio Maestro:
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications. 211-215 - Yuh-Shyan Hwang, Jiann-Jong Chen, Rong-Lian Shih, Yi-Tsen Ku:
A 2- μs Fast-Response Step-Up Converter With Efficiency-Enhancement Techniques Suitable for Cluster-Based Wireless Sensor Networks. 216-220
Volume 26, Number 2, February 2018
- Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li:
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. 221-229 - Kazuteru Namba, Fabrizio Lombardi:
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction. 230-238 - Shaoyi Peng, Han Zhou, Taeyoung Kim, Hai-Bao Chen, Sheldon X.-D. Tan:
Physics-Based Compact TDDB Models for Low-k BEOL Copper Interconnects With Time-Varying Voltage Stressing. 239-248 - Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun:
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling. 249-261 - Jui-Hung Hsieh, Hung-Ren Wang:
VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems. 262-271 - Albert Lee, Hochul Lee, Farbod Ebrahimi, Bonnie Lam, Wei-Hao Chen, Meng-Fan Chang, Pedram Khalili Amiri, Kang-Lung Wang:
A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories. 272-279 - Yizhi Wang, Jun Lin, Zhongfeng Wang:
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. 280-293 - Arnab Raha, Akhilesh Jaiswal, Syed Shakib Sarwar, Hrishikesh Jayakumar, Vijay Raghunathan, Kaushik Roy:
Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM. 294-307 - Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi:
Automatic Correction of Dynamic Power Management Architecture in Modern Processors. 308-318 - Sujuan Liu, Ning Lyu, Haojiang Wang:
The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection. 319-328 - Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg:
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. 329-340 - Aryan Tavakkoli, David B. Thomas:
A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers. 341-354 - Rahul Gharpinde, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Indranil Sengupta:
A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar. 355-366 - Jai Narayan Tripathi, Ramachandra Achar, Rakesh Malik:
Fast Analysis of Time Interval Error in Current-Mode Drivers. 367-377 - Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan:
Provably Good Max-Min-m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. 378-391 - Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl:
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. 392-403 - Daniel O'Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane:
Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs. 404-415 - Yan Song, Chi-Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, Rui Paulo Martins:
Passive Noise Shaping in SAR ADC With Improved Efficiency. 416-420
Volume 26, Number 3, March 2018
- Vasileios Leon, Georgios Zervakis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers. 421-430 - Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. 431-444 - Alok Prakash, Christopher T. Clarke, Siew-Kei Lam, Thambipillai Srikanthan:
Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design. 445-456 - Anteneh Gebregiorgis, Mehdi Baradaran Tahoori:
Fine-Grained Energy-Constrained Microprocessor Pipeline Design. 457-469 - Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory With Spin-Transfer Torque Magnetic RAM. 470-483 - Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung-Hyuk Kang, Yuan Xie:
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. 484-495 - Huyen Thi Pham, Hanho Lee:
Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. 496-507 - Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo:
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. 508-521 - Ja-Hoon Jin, Seok Kim, Xuefan Jin, Sang-Hoon Kim, Jung-Hoon Chun:
A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique. 522-530 - Shengcheng Wang, Taeyoung Kim, Zeyu Sun, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori:
Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs. 531-543 - Ganapati Bhat, Gaurav Singla, Ali K. Unver, Ümit Y. Ogras:
Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms. 544-557 - Vineeth Sarma, Rahul Thottathil, Bibhudatta Sahoo:
A DC-to-1-GHz Continuously Tunable Bandpass ADC. 558-571 - Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U:
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. 572-583 - Chunyu Peng, Songsong Xiao, Wenjuan Lu, Jingbo Zhang, Xiulong Wu, Junning Chen, Zhiting Lin:
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. 584-588 - Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan, Srinivas Theertham:
Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design. 589-593 - Xuan Dong, Lihong Zhang:
Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC. 594-598 - Arya Balachandran, Yong Chen, Chirn Chye Boon:
A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. 599-603 - Sahil Shah, Hakan Toreyin, Jennifer Hasler, Aishwarya Natarajan:
Temperature Sensitivity and Compensation on a Reconfigurable Platform. 604-607
Volume 26, Number 4, April 2018
- Hanwool Jeong, Tae Woo Oh, Seung Chul Song, Seong-Ook Jung:
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. 609-620 - Jen-Chieh Liu, Chao-Jen Huang, Pei-Ying Lee:
A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution. 621-629 - Karim Ali, Fei Li, Sunny Y. H. Lua, Chun-Huat Heng:
Energy- and Area-Efficient Spin-Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture. 630-638 - Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero:
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. 639-652 - Pawan Agarwal, Jong-Hoon Kim, Partha Pratim Pande, Deukhyoun Heo:
Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs. 653-662 - Ing-Jer Huang, Chun-Hung Lai, Yun-Chung Yang, Hsu-Kang Dow, Hung-Lun Chen:
A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory. 663-670 - Srivatsa Rangachar Srinivasa, Xueqing Li, Meng-Fan Chang, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan:
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration. 671-683 - Dongliang Chen, Jonathon Edstrom, Yifu Gong, Peng Gao, Lei Yang, Mark E. McCourt, Jinhui Wang, Na Gong:
Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory. 684-696 - Mario Donato Marino, Kuan-Ching Li:
RAMON: Region-Aware Memory Controller. 697-710 - Albert Ciprut, Eby G. Friedman:
Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors. 711-719 - Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li:
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. 720-732 - Wenjie Che, Fareena Saqib, Jim Plusquellic:
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF. 733-743 - Zimu Guo, Xiaolin Xu, Md. Tauhidur Rahman, Mark M. Tehranipoor, Domenic Forte:
SCARe: An SRAM-Based Countermeasure Against IC Recycling. 744-755 - Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez:
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. 756-767 - Cuiping Shao, Huiyun Li:
Identifying Single-Event Transient Location Based on Compressed Sensing. 768-777 - Katayoun Neshatpour, Wayne P. Burleson, Amin Khajeh, Houman Homayoun:
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence. 778-791 - Hakki Mert Torun, Madhavan Swaminathan, Anto Kavungal Davis, Mohamed Lamine Faycal Bellaredj:
A Global Bayesian Optimization Algorithm and Its Application to Integrated System Design. 792-802
Volume 26, Number 5, May 2018
- Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran:
The Cat and Mouse in Split Manufacturing. 805-817 - Ujjwal Guin, Ziqi Zhou, Adit D. Singh:
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. 818-830 - Maohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie:
Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications. 831-840 - Jaeha Kung, Duckhwan Kim, Saibal Mukhopadhyay:
Adaptive Precision Cellular Nonlinear Network. 841-854 - Jaemin Kim, Donghwa Shin, Nam Ik Cho, Byunghee Kang, Naehyuck Chang:
Aging Management Using a Reconfigurable Switch Network for Arrays of Nonideal Power Cells. 855-866 - Mohammad Fardad, Sayed Masoud Sayedi, Ehsan Yazdian:
Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals. 867-877 - Md. Hasanuzzaman, Bahareh Ghane Motlagh, Fayçal Mounaïm, Ahmad Hassan, Rabin Raut, Mohamad Sawan:
Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator. 878-891 - Qiong Wei Low, Mi Zhou, Liter Siek:
A Single-Stage Direct-Conversion AC-DC Converter for Inductively Powered Application. 892-902 - Jiann-Jong Chen, Yuh-Shyan Hwang, Jianhan Chen, Yi-Tsen Ku, Cheng-Chieh Yu:
A New Fast-Response Current-Mode Buck Converter With Improved I2-Controlled Techniques. 903-911 - Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Shu-Fei Tsai, Yiyu Shi:
Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits. 912-923 - Thinh Hung Pham, A. Prasad Vinod, A. S. Madhukumar:
A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications. 924-932 - Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. 933-944 - Yu-Kai Tsai, Yi-Keng Hsieh, Hung-Yu Tsai, Huan-Sheng Chen, Liang-Hung Lu:
A Concurrent Dual-Band and Dual-Mode Frequency Synthesizer for Radar Systems. 945-957 - Dong Wang, Pak Kwong Chan:
An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits. 958-968 - Chase Cook, Zeyu Sun, Ertugrul Demircan, Mehul D. Shroff, Sheldon X.-D. Tan:
Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method. 969-980 - Jürgen Freudenberger, Mohammed Rajab, Sergo Shavgulidze:
A Source and Channel Coding Approach for Improving Flash Memory Endurance. 981-990 - Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao:
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. 991-994 - Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian:
High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure. 995-999 - Supriya Chakraborty, Tinish Bhattacharya, Manan Suri:
Current Optimized Coset Coding for Efficient RRAM Programming. 1000-1004
Volume 26, Number 6, June 2018
- Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, Shih-Chieh Chang:
Contactless Testing for Prebond Interposers. 1005-1014 - Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate. 1015-1025 - Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya:
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks. 1026-1039 - Sumitha George, Xueqing Li, Minli Julie Liao, Kaisheng Ma, Srivatsa Rangachar Srinivasa, Karthik Mohan, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan:
Symmetric 2-D-Memory Access to Multidimensional Data. 1040-1050 - Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi:
Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs. 1051-1058 - Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón:
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. 1059-1072 - Zhangqing He, Meilin Wan, Jie Deng, Chuang Bai, Kui Dai:
A Reliable Strong PUF Based on Switched-Capacitor Circuit. 1073-1083 - Fatemeh Tehranipoor, Paul A. Wortman, Nima Karimian, Wei Yan, John A. Chandy:
DVFT: A Lightweight Solution for Power-Supply Noise-Based TRNG Using Dynamic Voltage Feedback Tuning System. 1084-1097 - Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang:
Stream Processing Dual-Track CGRA for Object Inference. 1098-1111 - Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu:
A Simple Yet Efficient Accuracy-Configurable Adder Design. 1112-1125 - Jun Liu, Beomsoo Park, Marino De Jesus Guzman, Ahmed Fahmy, Taewook Kim, Nima Maghari:
A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells. 1126-1138 - Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai:
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. 1139-1150 - Dong-Soo Lee, Sung-Jin Kim, Donggyu Kim, YoungGun Pu, Sang-Sun Yoo, Minjae Lee, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee:
A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator With Temperature Compensation and 15-dB Noise Reduction. 1151-1158 - Donghwa Shin, Massimo Poncino, Enrico Macii:
Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy. 1159-1170 - Yutong Ying, Xuefei Bai, Fujiang Lin:
A 1-Gb/s 6-10-GHz, Filterless, Pulsed UWB Transmitter With Symmetrical Waveform Analysis and Generation. 1171-1182 - Shanker Shreejith, Libin K. Mathew, A. Prasad Vinod, Suhaib A. Fahmy:
Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators. 1183-1191 - John S. Mincey, Eric C. Su, José Silva-Martínez, Christopher T. Rodenbeck:
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications. 1192-1203 - Georgios Zervakis, Fotios Ntouskas, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits. 1204-1208
Volume 26, Number 7, July 2018
- Ping-Lin Yang, Malgorzata Marek-Sadowska:
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. 1209-1222