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ORCIDNastaran Nemati
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2010 – 2019
- 2018
[j1]Nastaran Nemati
, Paul Beckett, Mark C. Reed, Karl M. Fant:
Clock-Less DFT-Less Test Strategy for Null Convention Logic. IEEE Trans. Emerg. Top. Comput. 6(4): 460-473 (2018)- 2016
- [c8]Nastaran Nemati, Mark C. Reed, Karl M. Fant, Paul Beckett:
Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic. ISCAS 2016: 746-749 - [c7]Nastaran Nemati, Mark C. Reed, Sri Parameswaran, Karl M. Fant:
Self-timed automatic test pattern generation for null convention logic. MWSCAS 2016: 1-4 - 2014
- [c6]Nastaran Nemati, Mark C. Reed, Michael R. Frater:
Asynchronous test hardware for Null Convention Logic. ISCAS 2014: 1744-1747 - 2011
- [c5]Nastaran Nemati, Zainalabedin Navabi:
Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. Asian Test Symposium 2011: 72-77 - 2010
- [c4]Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi:
Virtual tester development using HDL/PLI. EWDTS 2010: 412-415 - [c3]Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi:
Near optimal machine learning based random test generation. EWDTS 2010: 420-424 - [c2]Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi:
A mixed HDL/PLI test package. EWDTS 2010: 518-523
2000 – 2009
- 2009
- [c1]Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi:
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. DFT 2009: 268-276
Coauthor Index
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