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ORCIDShuai Wang 0006
Person information
- affiliation: Nanjing University, Department of Computer Science and Technology, China
- affiliation (PhD 2010): New Jersey Institute of Technology, Department of Electrical and Computer Engineering, Newark, NJ, USA
Other persons with the same name
- Shuai Wang — disambiguation page
- Shuai Wang 0001
![[0000-0003-3164-7002]](https://dblp.org/img/orcid-mark.12x12.png "0000-0003-3164-7002")
— Simula Research Laboratory, Oslo, Norway (and 1 more) - Shuai Wang 0002 — Chinese Academy of Sciences, Academy of Mathematics and Systems Science, NCMIS, Beijing, China
- Shuai Wang 0003 — Chinese Academy of Sciences, Shenyang Institute of Automation, State Key Laboratory of Robotics, China
- Shuai Wang 0004 — Chinese Academy of Sciences, Shenzhen Institute of Advanced Technology, China (and 2 more)
- Shuai Wang 0005 — Chinese Academy of Sciences, Institute of Automation, State Key Laboratory of Management and Control for Complex Systems, Beijing, China
- Shuai Wang 0007 — Tencent Robotics X, Shenzhen, China (and 1 more)
- Shuai Wang 0008 — Southeast University, School of Computer Science and Engineering, Nanjing, China (and 1 more)
- Shuai Wang 0009 — Sun Yat-sen University, Shenzhen, China (and 1 more)
- Shuai Wang 0010 — Ryerson University, Department of Electrical and Computer Engineering, Toronto, ON, Canada (and 1 more)
- Shuai Wang 0011 — Hong Kong University of Science and Technology, Hong Kong (and 2 more)
- Shuai Wang 0012 — Hong Kong Polytechnic University, Department of Computing, Hong Kong
- Shuai Wang 0013 — Beijing Institute of Technology, School of Information and Electronics, China
- Shuai Wang 0014 — Vrije Universiteit Amsterdam, The Netherlands (and 2 more)
- Shuai Wang 0015 — Wuhan University, School of Resource and Environmental Science, China
- Shuai Wang 0016 — Shanghai Jiao Tong University, Department of Computer Science and Engineering, China
- Shuai Wang 0017 — Tianjin University, Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, China
- Shuai Wang 0018 — University of Science and Technology of China, Department of Automation, Hefei, China
- Shuai Wang 0019 — Xidian University, State Key Laboratory of Integrated Service Networks, Xian, China
- Shuai Wang 0020 — University of Illinois at Chicago, Department of Computer Science, USA
- Shuai Wang 0021 — George Mason University, Department of Computer Science, Fairfax, VA, USA (and 1 more)
- Shuai Wang 0022 — SRI International, Center for Technology in Learning, Menlo Park, CA, USA (and 1 more)
- Shuai Wang 0023 — Changchun University of Science and Technology, School of Computer Science and Technology, China (and 1 more)
- Shuai Wang 0024 — Shenyang Agricultural University, College of Land and Environment, China (and 2 more)
- Shuai Wang 0025 — Changchun University of Science and Technology, School of Science, China
- Shuai Wang 0026 — Chinese Academy of Sciences, Aerospace Information Research Institute, Beijing, China (and 1 more)
- Shuai Wang 0027 — Beihang University, School of Computer Science and Engineering, Beijing, China (and 1 more)
- Shuai Wang 0028 — Tsinghua University, Department of Computer Science and Technology, Beijing, China
- Shuai Wang 0029 — Boston University, Division of Systems Engineering, Boston, MA, USA
- Shuai Wang 0030 — JOYY Inc, Beijing, China (and 2 more)
- Shuai Wang 0031 — China Three Gorges University, Key Laboratory of Intelligent Vision Based Monitoring for Hydroelectric Engineering, Yichang, China (and 1 more)
- Shuai Wang 0032 — University of Queensland, QLD, Australia
- Shuai Wang 0033 — Singapore University of Technology and Design, Information Systems Technology and Design Pillar, Tampines, Singapore (and 2 more)
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Journal Articles
- 2017
[j9]Shuai Wang, Guangshan Duan, Yupeng Li, Qianhao Dong:
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime. ACM Trans. Design Autom. Electr. Syst. 23(1): 4:1-4:18 (2017)- 2016
- [j8]Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan:
Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing. J. Circuits Syst. Comput. 25(9): 1650115:1-1650115:24 (2016) - 2015
- [j7]Shuai Wang, Guangshan Duan:
On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors. Microprocess. Microsystems 39(8): 686-692 (2015) - 2012
- [j6]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. IET Comput. Digit. Tech. 6(1): 50-58 (2012) - [j5]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 643-654 (2012) - 2009
- [j4]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Trans. Computers 58(9): 1171-1184 (2009) - [j3]Jie S. Hu, Shuai Wang, Sotirios G. Ziavras:
On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 953-963 (2009) - 2008
- [j2]Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras:
Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocess. Microsystems 32(3): 171-182 (2008) - [j1]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1503-1507 (2008)
Conference and Workshop Papers
- 2014
- [c14]Guangshan Duan, Shuai Wang:
Exploiting narrow-width values for improving non-volatile cache lifetime. DATE 2014: 1-4 - [c13]Chuanlei Zheng, Shuai Wang:
Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors. DFT 2014: 15-20 - 2013
- [c12]Shuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin:
Combating NBTI-induced aging in data caches. ACM Great Lakes Symposium on VLSI 2013: 215-220 - 2012
- [c11]Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan:
Low power aging-aware register file design by duty cycle balancing. DATE 2012: 546-549 - [c10]Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu:
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors. DFT 2012: 92-97 - 2011
- [c9]Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu:
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. ISVLSI 2011: 266-271 - 2010
- [c8]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. ISVLSI 2010: 310-315 - 2009
- [c7]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung:
Exploiting narrow-width values for thermal-aware register file designs. DATE 2009: 1422-1427 - 2008
- [c6]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI 2008: 81-86 - 2007
- [c5]Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras:
Asymmetrically Banked Value-Aware Register Files. ISVLSI 2007: 363-368 - [c4]Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu:
Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI 2007: 447-448 - 2006
- [c3]Jie S. Hu, Shuai Wang, Sotirios G. Ziavras:
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN 2006: 281-290 - [c2]Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS 2006: 14-20 - 2005
- [c1]Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras:
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference 2005: 200-214
Coauthor Index
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