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ORCIDDATE 2012: Dresden, Germany
- Wolfgang Rosenstiel, Lothar Thiele:
2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012. IEEE 2012, ISBN 978-1-4577-2145-8
Keynote Addresses
- Klaus Meder:
The mobile society - chances and challenges for micro- and power electronics. 1 - Mojy Chian:
New foundry models - accelerations in transformations of the semiconductor industry. 2
Validation of Modern Microprocessors
- Xiaoke Qin, Prabhat Mishra:
Automated generation of directed tests for transition coverage in cache coherence protocols. 3-8 - Eberle A. Rambo, Olav P. Henschel, Luiz C. V. dos Santos
:
On ESL verification of memory consistency for system-on-chip multiprocessing. 9-14 - Yoav Katz, Michal Rimon, Avi Ziv:
Generating instruction streams using abstract CSP. 15-20 - Timo Stripf, Ralf König, Jürgen Becker:
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture. 21-26 - Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li:
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. 27-32
Memory System Optimization
- Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. 33-38 - Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero:
TagTM - accelerating STMs with hardware tags for fast meta-data access. 39-44 - Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli:
Enabling dynamic assertion-based verification of embedded software through model-driven design. 212-217 - Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman:
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. 45-50 - Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
DRAM selection and configuration for real-time mobile systems. 51-56
Architectures and Efficient Designs for Automotive and Energy-Management Systems
- Jonas Rox, Rolf Ernst, Paolo Giusto:
Using timing analysis for the design of future switched based Ethernet automotive networks. 57-62 - Chun Zhang, Wei Wu, Hantao Huang, Hao Yu:
Fair energy resource allocation by minority game algorithm for smart buildings. 63-68 - Christoph Schmutzler, Martin Simons, Jürgen Becker:
On demand dependent deactivation of automotive ECUs. 69-74 - Michele Magno, Stevan Jovica Marinkovic, Davide Brunelli, Emanuel M. Popovici, Brendan O'Flynn, Luca Benini:
Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks. 75-80
Physical Design for Low-Power
- Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
IR-drop analysis of graphene-based power distribution networks. 81-86 - Keheng Huang, Yu Hu, Xiaowei Li, Bo Liu, Hongjin Liu, Jian Gong:
Off-path leakage power aware routing for SRAM-based FPGAs. 87-92 - Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara:
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. 93-98 - Mohammad Rahman, Carl Sechen:
Post-synthesis leakage power minimization. 99-104
Optimized Utilization of Embedded Platforms
- Andrea Marongiu, Paolo Burgio, Luca Benini:
Fast and lightweight support for nested parallelism on cluster-based embedded many-cores. 105-110 - Iraklis Anagnostopoulos, Alexandros Bartzas, Georgios Kathareios, Dimitrios Soudris:
A divide and conquer based distributed run-time mapping methodology for many-core platforms. 111-116 - Wen-Huei Lin, Li-Pin Chang:
Dual Greedy: Adaptive garbage collection for page-mapping solid-state disks. 117-122
Special Session - Hot Topic - EDA Solutions to New-Defect Detection in Advanced Process Technologies
- Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl:
EDA solutions to new-defect detection in advanced process technologies. 123-128
Beyond CMOS - Benchmarking for Future Technologies
- Clivia M. Sotomayor Torres, Jouni Ahopelto, Mart W. M. Graef, R. M. Popp, Wolfgang Rosenstiel:
Beyond CMOS - benchmarking for future technologies. 129-134
Effective Functional Simulation and Validation
- Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Accurately timed transaction level models for virtual prototyping at high abstraction level. 135-140 - Weiwei Chen, Xu Han, Rainer Dömer:
Out-of-order parallel simulation for ESL design. 141-146 - Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. 147-152 - Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco:
Approximating checkers for simulation acceleration. 153-158
Industrial Design Methodologies
- Dierk Steinbach:
Guidelines for model based systems engineering. 159-160 - Niccolò Battezzati, Stefano Colazzo, M. Maffione, L. Senepa:
SURF algorithm in FPGA: A novel architecture for high demanding industrial applications. 161-162 - Omar Hammami, Xinyu Li, Jean-Marc Brault:
NOCEVE: Network on chip emulation and verification environment. 163-164 - Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Richard Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo:
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. 165-166 - Tsunwai Gary Yip, Chuan Yung Hung, Venu Iyengar:
Challenges in verifying an integrated 3D design. 167-168
Large-Scale Energy and Thermal Management
- Yanzhi Wang, Qing Xie, Massoud Pedram, Younghyun Kim, Naehyuck Chang, Massimo Poncino:
Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems. 169-174 - Baris Aksanli, Tajana Simunic Rosing, Inder Monga:
Benefits of green energy and proportionality in high speed wide area networks connecting data centers. 175-180 - Andrea Bartolini, MohammadSadegh Sadri, John-Nicholas Furst, Ayse Kivilcim Coskun, Luca Benini:
Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer. 181-186 - Guanglei Liu, Ming Fan, Gang Quan:
Neighbor-aware dynamic thermal management for multi-core platform. 187-192
Model-Based Design and Verification for Embedded Systems
- Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal:
Playing games with scenario- and resource-aware SDF graphs through policy iteration. 194-199 - A. C. Rajeev, Swarup Mohalik, S. Ramesh:
Verifying timing synchronization constraints in distributed embedded architectures. 200-205 - Marco Di Natale, Haibo Zeng:
Task implementation of synchronous finite state machines. 206-211
Improving Reliability and Yield in Advanced Technologies
- Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
NBTI mitigation by optimized NOP assignment and insertion. 218-223 - Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
An accurate Single Event Effect digital design flow for reliable system level design. 224-229 - Mohammed Abdul Shahid:
Cross entropy minimization for efficient estimation of SRAM failure rate. 230-235
Hot Topic - Design Automation Tools for Engineering Biological Systems
- Boyan Yordanov, Evan Appleton, Rishi Ganguly, Ebru Aydin Gol, Swati Banerjee Carr, Swapnil Bhatia, Traci Haddock, Calin Belta, Douglas Densmore:
Experimentally driven verification of synthetic biological circuits. 236-241 - Soha Hassoun:
Genetic/bio design automation for (re-)engineering biological systems. 242-247
Interactive Presentations
- David Thach, Yutaka Tamiya, Shinya Kuwamura, Atsushi Ike:
Fast cycle estimation methodology for instruction-level emulator. 248-251 - Etem Deniz, Alper Sen, Jim Holt:
Verification coverage of embedded multicore applications. 252-255 - Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis:
Hazard driven test generation for SMT processors. 256-259 - Chundong Wang, Weng-Fai Wong:
Extending the lifetime of NAND flash memory by salvaging bad blocks. 260-263 - Suknam Kwon, Dongki Kim, Youngsik Kim, Sungjoo Yoo, Sunggu Lee:
A case study on the application of real phase-change RAM to main memory subsystem. 264-267 - Henning Sahlbach, Sean Whitty, Rolf Ernst:
A high-performance dense block matching solution for automotive 6D-vision. 268-271 - Mahsan Rofouei, Mohammad Ali Ghodrat, Miodrag Potkonjak, Alfonso Martinez-Nova:
Optimization intensive energy harvesting. 272-275 - Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich:
Designing FlexRay-based automotive architectures: A holistic OEM approach. 276-279 - Stephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker:
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems. 280-283 - Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
VaMV: Variability-aware Memory Virtualization. 284-287 - Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid:
Hybrid simulation for extensible processor cores. 288-291 - Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le:
Leveraging reconfigurability to raise productivity in FPGA functional debug. 292-295 - Markus Becker, Gilles B. Defo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, Sara Vinco:
MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution. 296-299 - Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan:
Run-time power-gating in caches of GPUs for leakage energy savings. 300-303 - Fei Sun:
Automatic generation of functional models for embedded processor extensions. 304-307 - Prakash Mohan Peranandam, Sachin Raviram, Manoranjan Satpathy, Anand Yeolekar, Ambar A. Gadkari, S. Ramesh:
An integrated test generation tool for enhanced coverage of Simulink/Stateflow models. 308-311 - Michaël Lafaye, Laurent Pautet, Etienne Borde, Marc Gatti, David Faura:
Model driven resource usage simulation for critical embedded systems. 312-315 - Min Li, Michael S. Hsiao:
RAG: An efficient reliability analysis of logic circuits on graphics processing units. 316-319
Routing Solutions for Upcoming NoC Challenges
- Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks. 320-325 - Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy:
An MILP-based aging-aware routing algorithm for NoCs. 326-331 - Sara Akbari, Ali Shafiee, Mahmood Fathy, Reza Berangi:
AFRA: A low cost high performance reliable routing for 3D mesh NoCs. 332-337
Industrial Embedded System Design
- Edoardo Patti, Andrea Acquaviva, Francesco Abate, Anna Osello, A. Cocuccio, Marco Jahn, Marc Jentsch, Enrico Macii:
Middleware services for network interoperability in smart energy efficient buildings. 338-339 - Mauro Turturici, Sergio Saponara, Luca Fanucci, Emilio Franchi:
Low-power embedded system for real-time correction of fish-eye automotive cameras. 340-341 - Monica Donno, Aleck Ferrari, Annalisa Scarpelli, Pietro Perlo, Alberto Bocca:
Mechatronic system for energy efficiency in bus transport. 342-343 - Mohammad Abdullah Al Faruque, Arquimedes Canedo:
Intelligent and collaborative embedded computing in automation engineering. 344-345
System-Level Power and Reliability Estimation and Optimization
- Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich:
Variation-aware leakage power model extraction for system-level hierarchical power analysis. 346-351 - Hai Wang, Sheldon X.-D. Tan, Xuexin Liu, Ashish Gupta:
Runtime power estimator calibration for high-performance microprocessors. 352-357 - Norbert Druml, Christian Steger, Reinhold Weiss, Andreas Genser, Josef Haid:
Estimation based power and supply voltage management for future RF-powered multi-core smart cards. 358-363 - Haroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii:
Application-specific memory partitioning for joint energy and lifetime optimization. 364-369
Embedded Tutorial - State-of-the-Art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems
- Marius Bozga, Alexandre David, Arnd Hartmanns, Holger Hermanns, Kim G. Larsen, Axel Legay, Jan Tretmans:
State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systems. 370-375
Compilers and Source-Level Simulation
- Stefan Stattelmann, Gernot Gebhard, Christoph Cullmann, Oliver Bringmann, Wolfgang Rosenstiel:
Hybrid source-level simulation of data caches using abstract cache models. 376-381 - Zhonglei Wang, Jörg Henkel:
Accurate source-level simulation of embedded software with respect to compiler optimizations. 382-387 - Dongrui She, Yifan He, Bart Mesman, Henk Corporaal:
Scheduling for register file energy minimization in explicit datapath architectures. 388-393 - Daniel Cordes, Peter Marwedel:
Multi-objective aware extraction of task-level parallelism using genetic algorithms. 394-399
Advances in Test Generation
- Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov:
RTL analysis and modifications for improving at-speed test. 400-405 - Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil:
Test generation for clock-domain crossing faults in integrated circuits. 406-411 - Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
A new SBST algorithm for testing the register file of VLIW processors. 412-417 - Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian:
On the optimality of K longest path generation algorithm under memory constraints. 418-423
Special Day E-Mobility - Embedded Systems and SW Challenges
- Samarjit Chakraborty, Martin Lukasiewycz, Christian Buckl, Suhaib A. Fahmy, Naehyuck Chang, Sangyoung Park, Younghyun Kim, Patrick Leteinturier, Hans Adlkofer:
Embedded systems and software challenges in electric vehicles. 424-429
Panel - Accelerators and Emulatiors for HS Verification
- Bashir M. Al-Hashimi, Ronny Morad:
Accelerators and emulators: Can they become the platform of choice for hardware verification? 430
Medical and Healthcare Applications
- Mohammed Shoaib, Gene Marsh, Harinath Garudadri, Somdeb Majumdar:
A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoring. 431-436 - Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. 437-442 - Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng:
A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system. 443-448
Microarchitecture
- Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng:
Energy-efficient branch prediction with Compiler-guided History Stack. 449-454 - Maryam Sadooghi-Alvandi, Kaveh Aasaraai, Andreas Moshovos:
Toward virtualizing branch direction prediction. 455-460 - Xianglei Dang, Xiaoyin Wang, Dong Tong, Junlin Lu, Jiangfang Yi, Keyi Wang:
S/DC: A storage and energy efficient data prefetcher. 461-466 - Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
An architecture-level approach for mitigating the impact of process variations on extensible processors. 467-472
Shared Memory Management in Multicore
- Konstantinos Aisopos, Jaideep Moses, Ramesh Illikkal, Ravishankar R. Iyer, Donald Newell:
PCASA: Probabilistic control-adjusted Selective Allocation for shared caches. 473-478 - Abhishek Das, Matthew Schuchhardt, Nikos Hardavellas, Gokhan Memik, Alok N. Choudhary:
Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores. 479-484 - Fazal Hameed, Lars Bauer, Jörg Henkel:
Dynamic cache management in multi-core architectures through run-time adaptation. 485-490 - José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini:
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. 491-496
Scheduling and Allocation
- José Marinho, Vincent Nélis, Stefan M. Petters, Isabelle Puaut:
Preemption delay analysis for floating non-preemptive region scheduling. 497-502 - Ming Fan, Gang Quan:
Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform. 503-508 - Jia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois C. Knoll:
Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving. 509-514 - Sophie Quinton, Matthias Hanke, Rolf Ernst:
Formal analysis of sporadic overload in real-time systems. 515-520
Testing of Non-Volatile Memories
- Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai:
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. 521-526 - Jin Zha, Xiaole Cui, Chung Len Lee:
Modeling and testing of interference faults in the nano NAND Flash memory. 527-531 - Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. 532-537
Interactive Presentations
- Fahimeh Jafari, Axel Jantsch, Zhonghai Lu:
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling. 538-541 - Giorgos Dimitrakopoulos, Emmanouil Kalligeros:
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches. 542-545 - Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan:
Low power aging-aware register file design by duty cycle balancing. 546-549 - Nainala Vyagrheswarudu, Subrangshu Das, Abhishek Ranjan:
PowerAdviser: An RTL power platform for interactive sequential optimizations. 550-553 - Arquimedes Canedo, Mohammad Abdullah Al Faruque:
Towards parallel execution of IEC 61131 industrial cyber-physical systems applications. 554-557 - Kameshwar Chandrasekar, Supratik K. Misra, Sanjay Sengupta, Michael S. Hsiao:
A scan pattern debugger for partial scan industrial designs. 558-561 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri:
FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs. 562-565 - Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer:
Exploiting binary translation for fast ASIP design space exploration on FPGAs. 566-569 - Cedric Walravens, Wim Dehaene:
Design of a low-energy data processing architecture for WSN nodes. 570-573 - Hamed Tabkhi, Gunar Schirner:
Application-specific power-efficient approach for reducing register file vulnerability. 574-577 - Raphael Guerra, Gerhard Fohler:
On-line scheduling of target sensitive periodic tasks with the gravitational task model. 578-581