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2010 – 2019
- 2015
[j11]Yiqiang Ding, Wei Zhang:
Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing. J. Comput. Sci. Eng. 9(4) (2015)- 2014
- [j10]Lan Wu, Yiqiang Ding, Wei Zhang:
Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors. J. Comput. Sci. Eng. 8(1): 25-33 (2014) - [j9]Wei Zhang, Yiqiang Ding:
Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability. J. Comput. Sci. Eng. 8(1): 34-42 (2014) - [c9]Yiqiang Ding, Wei Zhang:
Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency. EUC 2014: 52-57 - [c8]Lan Wu, Yiqiang Ding, Wei Zhang:
Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. HPCC/CSS/ICESS 2014: 526-533 - [c7]Yiqiang Ding, Wei Zhang:
Bounding the Worst-Case Execution Time of Static NUCA Caches. HPCC/CSS/ICESS 2014: 1181-1184 - [c6]Yiqiang Ding, Wei Zhang:
WCET analysis of static NUCA caches. IPCCC 2014: 1-6 - 2013
- [j8]Yiqiang Ding, Lan Wu, Wei Zhang:
Bounding Worst-Case DRAM Performance on Multicore Processors. J. Comput. Sci. Eng. 7(1): 53-66 (2013) - [j7]Yiqiang Ding, Wei Zhang:
Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. J. Comput. Sci. Eng. 7(1): 67-80 (2013) - [j6]Yiqiang Ding, Wei Zhang:
Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches. J. Comput. Sci. Eng. 7(4): 285-299 (2013) - [c5]Wei Zhang, Yiqiang Ding:
Standard deviation of CPI: A new metric to evaluate architectural time predictability. ASAP 2013: 111-112 - [c4]Wei Zhang, Yiqiang Ding:
Hybrid SPM-cache architectures to achieve high time predictability and performance. ASAP 2013: 297-304 - [c3]Yiqiang Ding, Wei Zhang:
On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. ISQED 2013: 627-634 - 2012
- [j5]Yiqiang Ding, Wei Zhang:
Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. J. Comput. Sci. Eng. 6(1): 12-25 (2012) - [j4]Yiqiang Ding, Wei Zhang:
Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. SIGBED Rev. 9(4): 6-15 (2012) - 2011
- [c2]Yiqiang Ding, Wei Zhang:
Multicore-Aware Code Positioning to Improve Worst-Case Performance. ISORC 2011: 225-232 - 2010
- [j3]Yiqiang Ding, Wei Zhang:
Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. IEEE Trans. Computers 59(6): 855-864 (2010) - [c1]Yiqiang Ding, Wei Zhang:
Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. ACM Southeast Regional Conference 2010: 108
2000 – 2009
- 2009
- [j2]Yiqiang Ding, Jun Yan, Wei Zhang:
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. J. Comput. Sci. Eng. 3(1): 59-71 (2009)
1990 – 1999
- 1999
- [j1]Yiqiang Ding:
An improvement of GNY logic for the reflection attacks. J. Comput. Sci. Technol. 14(6): 619-623 (1999)
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