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ORCIDChushin Afuso
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1990 – 1999
- 1995
[j5]Yasunori Nagata, Masao Mukaidono, Chushin Afuso:
An Optimum Half-Hot Code Assignment Algorithm for Input Encoding and Its Application to Finite State Machines. IEICE Trans. Inf. Syst. 78-D(10): 1231-1238 (1995)- 1993
- [c1]Yasunori Nagata, Chushin Afuso:
A Method of Test Pattern Generation for Multiple-Valued PLA's. ISMVL 1993: 87-91 - 1992
- [j4]Chotei Zukeran, Yasunori Nagata, Chushin Afuso, Makoto Honda, Yutaka Nagamine:
A universal literal circuit and its application to quaternary logic networks. Syst. Comput. Jpn. 23(2): 39-50 (1992) - 1990
- [j3]Yasunori Nagata, Chotei Zukeran, Chushin Afuso:
A State Assignment for p-Valued Sequential Machines. Syst. Comput. Jpn. 21(3): 93-100 (1990)
1980 – 1989
- 1987
- [j2]Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi:
Design of micropower CMOS quaternary memory circuits. Syst. Comput. Jpn. 18(11): 61-69 (1987) - 1986
- [j1]Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi:
Design of low-power quaternary CMOS logic circuits. Syst. Comput. Jpn. 17(3): 93-101 (1986)
1960 – 1969
- 1968
- [b1]Chushin Afuso:
Analog Computation With Random Pulse Sequences. University of Illinois Urbana-Champaign, USA, 1968
Coauthor Index
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