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Jakob Lechner
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2020 – today
- 2020
- [j1]Georgy Lukyanov, Andrey Mokhov, Jakob Lechner:
Formal Verification of Spacecraft Control Programs. ACM Trans. Embed. Comput. Syst. 19(5): 37:1-37:18 (2020)
2010 – 2019
- 2019
- [c16]Andrey Mokhov, Georgy Lukyanov, Jakob Lechner:
Formal verification of spacecraft control programs (experience report). Haskell@ICFP 2019: 139-145 - 2018
- [c15]Markus Schütz, Andreas Steininger
, Florian Huemer
, Jakob Lechner:
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT 2018: 1-6 - [i1]Andrey Mokhov, Georgy Lukyanov, Jakob Lechner:
Formal Verification of Spacecraft Control Programs Using a Metalanguage for State Transformers. CoRR abs/1802.01738 (2018) - 2016
- [c14]Florian Huemer
, Jakob Lechner, Andreas Steininger
:
A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD 2016: 392-395 - 2015
- [c13]Jakob Lechner, Andreas Steininger
, Florian Huemer
:
Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD 2015: 519-526 - 2014
- [c12]Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger
:
Protection of Muller-Pipelines from transient faults. ISQED 2014: 123-131 - 2013
- [c11]Jakob Lechner, Varadan Savulimedu Veeravalli:
Modular Redundancy in a GALS System Using Asynchronous Recovery Links. ASYNC 2013: 23-30 - [c10]Syed Rameez Naqvi, Andreas Steininger
, Jakob Lechner:
An SET Tolerant Tree Arbiter Cell. ASYNC 2013: 31-39 - 2012
- [c9]Jakob Lechner, Martin Lampacher, Thomas Polzer:
A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. ACSD 2012: 122-131 - [c8]Jakob Lechner:
Designing Robust GALS Circuits with Triple Modular Redundancy. EDCC 2012: 227-236 - [c7]Jakob Lechner, Martin Lampacher:
Protecting pipelined asynchronous communication channels against single event upsets. ICCD 2012: 480-481 - [c6]Thomas Polzer, Andreas Steininger
, Jakob Lechner:
Muller C-Element Metastability Containment. PATMOS 2012: 103-112 - [c5]Jakob Lechner, Robert Najvirt:
A Generic Architecture for Robust Asynchronous Communication Links. PATMOS 2012: 121-130 - 2010
- [c4]Marcus Jeitler, Jakob Lechner, Andreas Steininger
:
Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS 2010: 233-236 - [c3]Marcus Jeitler, Jakob Lechner:
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. DSD 2010: 219-225
2000 – 2009
- 2009
- [c2]Marcus Jeitler, Jakob Lechner:
Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. MEMICS 2009 - [c1]Marcus Jeitler, Jakob Lechner:
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. ReConFig 2009: 65-70
Coauthor Index
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