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ORCIDNicky Lu
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2020 – today
- 2021
[c7]Nicky Lu:
Optimizing Monolithic and Heterogeneous Integration to Create Intelligent-Grand-Scale-Integration for Smart MicroSystems. DRC 2021: 1-2- [c6]Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen:
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c5]Chun Shiah, C. N. Chang, Richard Crisp, C. P. Lin, C. N. Pan, C. P. Chuang, H. L. Chen, S. H. Jheng, T. F. Chang, W. J. Huang, K. C. Ting, Rick Dai, W. M. Huang, Bor-Doou Rong, Nicky Lu:
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. VLSI Circuits 2019: 116- - 2015
- [c4]Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima
, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu:
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC 2015: 186- - 2011
- [c3]Nicky Lu, Leland Chang, Daisaburo Takashima:
Future system and memory architectures: Transformations by technology and applications. ISSCC 2011: 530
2000 – 2009
- 2008
- [j1]Nicky Lu, Shyh-Jye Jou:
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07). IEEE J. Solid State Circuits 43(11): 2352-2353 (2008) - [c2]Sreedhar Natarajan, Nicky Lu:
Private Equity: Fight them or Invite them. ISSCC 2008: 156-157 - 2007
- [c1]Nicky Lu, C. K. Wang, Philip Wong, Sreedhar Natarajan:
E1 Ultimate Limits of Integrated Electronics. ISSCC 2007: 146-147
Coauthor Index
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