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2020 – today
- 2024
[j49]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams. IEICE Trans. Inf. Syst. 107(8): 922-929 (2024)- 2023
- [j48]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Representation of Maximally Asymmetric Functions Based on Decision Diagrams. FLAP 10(6): 1105-1130 (2023) - [c54]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Decomposition-Based Representation of Symmetric Multiple-Valued Functions. ISMVL 2023: 76-81 - [i1]Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama:
On the distribution of sensitivities of symmetric Boolean functions. CoRR abs/2306.14401 (2023) - 2022
- [j47]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions. J. Multiple Valued Log. Soft Comput. 38(3-4): 387-405 (2022) - [c53]Jon T. Butler, Tsutomu Sasao:
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions. ISMVL 2022: 125-130 - [c52]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Decision Diagrams for Maximally Asymmetric Functions. ISMVL 2022: 164-169 - 2021
- [c51]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions. ISMVL 2021: 13-18 - [c50]Tsutomu Sasao, Jon T. Butler:
Linear Decompositions for Multi-Valued Input Classification Functions. ISMVL 2021: 19-25 - 2020
- [c49]Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama:
Properties of Multiple-Valued Partition Functions. ISMVL 2020: 82-87 - [c48]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Optimum Linear Decomposition of Symmetric Index Generation Functions. ISMVL 2020: 130-136
2010 – 2019
- 2019
- [c47]Jon T. Butler, Tsutomu Sasao:
Realizing all Index Generation Functions by the Row-Shift Method. ISMVL 2019: 138-143 - [c46]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions. ISMVL 2019: 144-149 - [c45]Jon T. Butler, Tsutomu Sasao:
Maximally Asymmetric Multiple-Valued Functions. ISMVL 2019: 188-193 - 2018
- [j46]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions. FLAP 5(9): 1849-1866 (2018) - [c44]Jon T. Butler, Tsutomu Sasao:
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions. ISMVL 2018: 138-143 - [c43]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. ISMVL 2018: 144-149 - [p1]Tsutomu Sasao, Jon T. Butler:
Decomposition of Index Generation Functions Using a Monte Carlo Method. Advanced Logic Synthesis 2018: 209-225 - 2017
- [j45]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions. IEICE Trans. Inf. Syst. 100-D(8): 1583-1591 (2017) - [c42]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions. ISMVL 2017: 161-166 - 2016
- [j44]Jon T. Butler, Tsutomu Sasao:
A set partition number system. Australas. J Comb. 65: 152-169 (2016) - [j43]Vincent C. Gaudet
, Jon T. Butler, Robert Wille, Naofumi Homma:
Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 1-4 (2016) - [j42]Carole J. Etherington, Matthew W. Anderson, Eric Bach, Jon T. Butler, Pantelimon Stanica:
A Parallel Approach in Computing Correlation Immunity up to Six Variables. Int. J. Found. Comput. Sci. 27(4): 511- (2016) - [c41]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Efficient Heuristic for Linear Decomposition of Index Generation Functions. ISMVL 2016: 96-101 - 2015
- [j41]Jon T. Butler, Tsutomu Sasao:
High-Speed Hardware Partition Generation. ACM Trans. Reconfigurable Technol. Syst. 7(4): 28:1-28:17 (2015) - [c40]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. ISMVL 2015: 170-175 - 2014
- [b2]Tsutomu Sasao, Jon T. Butler:
Applications of Zero-Suppressed Decision Diagrams. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2014, ISBN 978-3-031-79869-6, pp. 1-123 - [j40]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. IEICE Trans. Inf. Syst. 97-D(9): 2234-2242 (2014) - [j39]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components. J. Multiple Valued Log. Soft Comput. 22(1-2): 59-78 (2014) - [j38]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators. J. Multiple Valued Log. Soft Comput. 23(3-4): 293-313 (2014) - [c39]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. ISMVL 2014: 190-195 - 2013
- [c38]Jon T. Butler, Tsutomu Sasao:
Hardware Index to Set Partition Converter. ARC 2013: 72-83 - [c37]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. ISMVL 2013: 284-289 - 2012
- [c36]Jon T. Butler, Tsutomu Sasao:
Hardware Index to Permutation Converter. IPDPS Workshops 2012: 431-436 - [c35]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. ISMVL 2012: 122-127 - 2011
- [j37]Jon T. Butler, C. L. Frenzen, Njuguna Macaria, Tsutomu Sasao:
A fast segmentation algorithm for piecewise polynomial numeric function generators. J. Comput. Appl. Math. 235(14): 4076-4082 (2011) - [c34]Jon T. Butler, Tsutomu Sasao:
Index to Constant Weight Codeword Converter. ARC 2011: 193-205 - [c33]Jon T. Butler, Tsutomu Sasao:
Fast Hardware Computation of x Mod z. IPDPS Workshops 2011: 294-297 - [c32]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numeric Function Generators Using Piecewise Arithmetic Expressions. ISMVL 2011: 16-21 - 2010
- [j36]Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. 93-D(8): 2026-2035 (2010) - [j35]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. IEICE Trans. Inf. Syst. 93-D(8): 2059-2067 (2010) - [j34]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. Inf. Media Technol. 5(2): 412-423 (2010) - [j33]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. IPSJ Trans. Syst. LSI Des. Methodol. 3: 118-129 (2010) - [j32]C. L. Frenzen, Tsutomu Sasao, Jon T. Butler:
On the number of segments needed in a piecewise linear approximation. J. Comput. Appl. Math. 234(2): 437-446 (2010) - [c31]J. L. Shafer, S. W. Schneider, Jon T. Butler, Pantelimon Stanica:
Enumeration of Bent Boolean Functions by Reconfigurable Computer. FCCM 2010: 265-272 - [c30]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. ISMVL 2010: 223-228
2000 – 2009
- 2009
- [b1]Tsutomu Sasao, Jon T. Butler:
Progress in Applications of Boolean Functions. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2009, ISBN 978-3-031-79811-5 - [c29]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. ISMVL 2009: 349-355 - [c28]Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL 2009: 362-369 - 2008
- [c27]Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao:
Programmable Numerical Function Generators for Two-Variable Functions. DSD 2008: 891-898 - [c26]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical function generators using bilinear interpolation. FPL 2008: 463-466 - 2007
- [j31]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2752-2761 (2007) - [j30]Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler:
Numerical Function Generators Using LUT Cascades. IEEE Trans. Computers 56(6): 826-838 (2007) - [c25]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ASP-DAC 2007: 535-540 - [c24]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. DSD 2007: 280-287 - 2006
- [j29]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3510-3518 (2006) - [c23]Hui Qin, Tsutomu Sasao, Jon T. Butler:
Implementation of LPM Address Generators on FPGAs. ARC 2006: 170-181 - [c22]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. ASP-DAC 2006: 378-383 - [c21]Tsutomu Sasao, Jon T. Butler:
Implementation of Multiple-Valued CAM Functions by LUT Cascades. ISMVL 2006: 11 - 2005
- [j28]Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler:
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. J. Multiple Valued Log. Soft Comput. 11(5-6): 437-465 (2005) - [j27]Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura:
Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54(9): 1041-1053 (2005) - [c20]Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler:
Programmable Numerical Function Generators: Architectures and Synthesis Method. FPL 2005: 118-123 - 2004
- [c19]Tsutomu Sasao, Jon T. Butler:
A fast method to derive minimum SOPs for decomposable functions. ASP-DAC 2004: 585-590 - 2003
- [c18]Jon T. Butler, Tsutomu Sasao:
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. ISMVL 2003: 383-390 - 2002
- [j26]Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi:
Bi-Partition of Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2693-2700 (2002) - 2001
- [j25]Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko:
On the number of generators for transeunt triangles. Discret. Appl. Math. 108(3): 309-316 (2001) - [j24]Tsutomu Sasao, Jon T. Butler:
Worst and Best Irredundant Sum-of-Products Expressions. IEEE Trans. Computers 50(9): 935-948 (2001) - [c17]Tsutomu Sasao, Jon T. Butler:
On the minimization of SOPs for bi-decomposition functions. ASP-DAC 2001: 219-224 - 2000
- [j23]Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich:
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1386-1388 (2000) - [c16]Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko:
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL 2000: 141-146
1990 – 1999
- 1998
- [c15]Jon T. Butler, Tsutomu Sasao:
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. ISMVL 1998: 83-88 - 1997
- [j22]Kriss A. Schueller, Jon T. Butler:
Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. IEEE Trans. Computers 46(2): 205-209 (1997) - [j21]Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III:
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. IEEE Trans. Computers 46(4): 491-494 (1997) - [c14]Tsutomu Sasao, Jon T. Butler:
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. ISMVL 1997: 55-60 - 1996
- [c13]Jon T. Butler, J. L. Nowlin, Tsutomu Sasao:
Planarity in ROMDD's of Multiple-Valued Symmetric Functions. ISMVL 1996: 236-241 - [c12]Tsutomu Sasao, Jon T. Butler:
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. ISMVL 1996: 248-254 - 1995
- [c11]Tsutomu Sasao, Jon T. Butler:
Planar Multiple-Valued Decision Diagrams. ISMVL 1995: 28-35 - 1994
- [c10]Gerhard W. Dueck, Jon T. Butler:
Multiple-Valued Logic Operations with Universal Literals. ISMVL 1994: 73-79 - [c9]Tsutomu Sasao, Jon T. Butler:
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. ISMVL 1994: 97-106 - [c8]Jon T. Butler, Tsutomu Sasao:
Multiple-Valued Combinational Circuits with Feedback. ISMVL 1994: 342-347 - 1993
- [c7]Cem Yildirim, Jon T. Butler, Chyan Yang:
Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. ISMVL 1993: 17-23 - 1992
- [j20]Kriss A. Schueller, Jon T. Butler:
On the Design of Cost-Tables for Realizing Multiple-Valued Circuits. IEEE Trans. Computers 41(2): 178-189 (1992) - [c6]Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler:
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74 - [c5]Susan W. Butler, Jon T. Butler:
Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. ISMVL 1992: 372-379 - 1991
- [j19]Parthasarathy P. Tirumalai, Jon T. Butler:
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. IEEE Trans. Computers 40(2): 167-177 (1991) - [c4]Jon T. Butler, Kriss A. Schueller:
Worst Case Number of Terms in Symmetric Multiple-Valued Functions. ISMVL 1991: 94-101 - [c3]Young-hoon Chang, Jon T. Butler:
The Design of Current Mode CMOS Multiple-Valued Circuits. ISMVL 1991: 130-138 - 1990
- [j18]Jon T. Butler, Kriss A. Schueller:
On the Equivalence of Cost Functions in the Design of Circuits by Costtable. IEEE Trans. Computers 39(6): 842-844 (1990) - [j17]Joo-Kang Lee, Jon T. Butler:
A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs. IEEE Trans. Computers 39(10): 1298-1304 (1990) - [c2]John M. Yurchak, Jon T. Butler:
HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. ISMVL 1990: 144-152 - [c1]Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer:
A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. ISMVL 1990: 286-291
1980 – 1989
- 1989
- [j16]Edward A. Bender, Jon T. Butler:
On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions. IEEE Trans. Computers 38(1): 82-98 (1989) - 1988
- [j15]Jon T. Butler:
Multiple-Valued Logic - Guest Editor's Introduction. Computer 21(4): 13-15 (1988) - [j14]Jon T. Butler, Hans G. Kerkhoff:
Multiple-Valued CCD Circuits. Computer 21(4): 58-69 (1988) - 1985
- [j13]Edward A. Bender, Jon T. Butler:
Enumeration of Structured Flowcharts. J. ACM 32(3): 537-548 (1985) - 1982
- [j12]Jon T. Butler:
On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems. Inf. Sci. 28(1): 63-67 (1982) - 1981
- [j11]Jon T. Butler:
Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms. IEEE Trans. Computers 30(8): 590-596 (1981) - 1980
- [j10]Patrick E. White, Jon T. Butler:
Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs. Inf. Control. 46(3): 241-256 (1980)
1970 – 1979
- 1979
- [j9]Jon T. Butler:
Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps. Inf. Control. 43(3): 304-326 (1979) - [j8]Jon T. Butler:
Decomposable Maps in General Tessellation Structures. J. Comput. Syst. Sci. 18(1): 1-7 (1979) - 1978
- [j7]Jon T. Butler:
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates. J. ACM 25(3): 481-498 (1978) - [j6]Jon T. Butler:
Tandem Networks of Universal Cells. IEEE Trans. Computers 27(9): 785-799 (1978) - [j5]Edward A. Bender, Jon T. Butler:
Asymptotic Aproximations for the Number of Fanout-Free Functions. IEEE Trans. Computers 27(12): 1180-1183 (1978) - 1976
- [j4]Jon T. Butler:
Restricted Cellular Networks. IEEE Trans. Computers 25(11): 1139-1142 (1976) - 1975
- [j3]Jon T. Butler:
On the Number of Functions Realized by Cascades and Disjunctive Networks. IEEE Trans. Computers 24(7): 681-690 (1975) - 1974
- [j2]Jon T. Butler:
A Note on Cellular Automata Simulations. Inf. Control. 26(3): 286-295 (1974) - 1973
- [j1]Jon T. Butler, Kenneth J. Breeding:
Some Characteristics of Universal Cell Nets. IEEE Trans. Computers 22(10): 897-903 (1973)
Coauthor Index
[j49] [j48] [c54] [i1] [j47] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [j46] [c44] [c43] [p1] [j45] [c42] [j44] [c41] [j41] [c40] [b2] [j40] [j39] [j38] [c39] [c38] [c37] [c36] [c35] [j37] [c34] [c33] [c32] [j36] [j35] [j34] [j33] [j32] [c30] [b1] [c29] [c28] [c27] [c26] [j31] [j30] [c25] [c24] [j29] [c23] [c22] [c21] [j28] [j27] [c20] [c19] [c18] [j26] [j24] [c17] [c15] [j21] [c14] [c13] [c12] [c11] [c9] [c8]
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