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2010 – 2019
- 2012
[j6]W.-H. Hu, C.-Y. Chen, Jun Ho Bahn, Nader Bagherzadeh
:
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. IET Comput. Digit. Tech. 6(2): 86-94 (2012)- 2010
- [j5]Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh:
Parallel processing for block ciphers on a fault tolerant networked processor array. Int. J. High Perform. Syst. Archit. 2(3/4): 156-167 (2010)
2000 – 2009
- 2009
- [j4]Jun Ho Bahn, Jungsook Yang, Wen-Hsiang Hu, Nader Bagherzadeh:
Parallel FFT Algorithms on Network-on-Chips. J. Circuits Syst. Comput. 18(2): 255-269 (2009) - [c8]Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh:
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. ITNG 2009: 849-854 - [c7]Wen-Hsiang Hu, Jun Ho Bahn, Nader Bagherzadeh:
Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. SBAC-PAD 2009: 35-40 - 2008
- [j3]Jun Ho Bahn, Nader Bagherzadeh:
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. IET Comput. Digit. Tech. 2(1): 63-73 (2008) - [j2]Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh:
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. Parallel Process. Lett. 18(2): 239-255 (2008) - [c6]Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh:
A Generic Network Interface Architecture for a Networked Processor Array (NePA). ARCS 2008: 247-260 - [c5]Jun Ho Bahn, Nader Bagherzadeh:
Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture. CSICC 2008: 98-105 - [c4]Wolfgang Trumler, Sebastian Schlingmann, Theo Ungerer, Jun Ho Bahn, Nader Bagherzadeh:
Self-optimized Routing in a Network on-a-Chip. BICC 2008: 199-212 - [c3]Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh:
Parallel FFT Algorithms on Network-on-Chips. ITNG 2008: 1087-1093 - 2007
- [j1]Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh:
Design of a router for network-on-chip. Int. J. High Perform. Syst. Archit. 1(2): 98-105 (2007) - [c2]Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh:
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. ITNG 2007: 1033-1038 - [c1]Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh:
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). SBAC-PAD 2007: 211-218
Coauthor Index
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