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ORCIDLiang Fang 0008
Person information
- affiliation: National Key Laboratory for High Performance Computing, Changsha, Hunan, China
Other persons with the same name
- Liang Fang — disambiguation page
- Liang Fang 0001
![[0009-0007-8102-0677]](https://dblp.org/img/orcid-mark.12x12.png "0009-0007-8102-0677")
— Shihezi University, Shihezi, Xinjiang, China - Liang Fang 0002 — Nanchang Hangkong University, Nanchang, China
- Liang Fang 0003 — Beijing Forestry University, Beijing, China
- Liang Fang 0004 — Imperial College London, London, UK
- Liang Fang 0005 — Harbin Engineering University, Harbin, Heilongjiang, China
- Liang Fang 0006 — Southern Methodist University, Dallas, TX, USA
- Liang Fang 0007 — Yanan University, Yanan, China
- Liang Fang 0009 — Institute of Information Engineering, Chinese Academy of Sciences, Beijing, China
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2020 – today
- 2025
[j7]Nuo Xu, Yihong Hu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang:
ILOSSS - Improved Logic Synthesis based on Several Stateful Logic Gates. ACM Trans. Design Autom. Electr. Syst. 30(4): 60:1-60:23 (2025)- 2024
- [c3]Yihong Hu, Nuo Xu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang:
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing. ASPDAC 2024: 805-811 - 2023
- [j6]Chenglong Huang, Nuo Xu, Junwei Zeng, Wenqing Wang, Yihong Hu, Liang Fang, Desheng Ma, Yanting Chen:
Rescuing ReRAM-based Neural Computing Systems from Device Variation. ACM Trans. Design Autom. Electr. Syst. 28(1): 6:1-6:17 (2023) - [j5]Junwei Zeng, Nuo Xu, Yabo Chen, Chenglong Huang, Zhiwei Li, Liang Fang:
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device. ACM Trans. Design Autom. Electr. Syst. 28(1): 8:1-8:16 (2023) - 2022
- [j4]Junwei Zeng, Nuo Xu, Cheng Li, Desheng Ma, Chenglong Huang, Wenqing Wang, Yihong Hu, Liang Fang:
MESO-LUT: A design approach of look up tables based on MESO devices. Microelectron. J. 126: 105493 (2022) - [j3]Pinyun Yi, Yuhua Liang, Shubin Liu, Nuo Xu, Liang Fang, Yue Hao:
A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 859-863 (2022) - 2021
- [c2]Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Juan Bautista Roldán, Mireia Bargallo González, Francesca Campabadal, Liang Fang:
Simulation of serial RRAM cell based on a Verilog-A compact model. DCIS 2021: 1-6 - [c1]Junhao Zhu, Kaixin Huang, Xiaomin Zou, Chenglong Huang, Nuo Xu, Liang Fang:
HDNH: a read-efficient and write-optimized hashing scheme for hybrid DRAM-NVM memory. ICPP 2021: 47:1-47:10 - 2020
- [j2]Nuo Xu, Tae Gyun Park, Hae Jin Kim, Xinglong Shao, Kyung Jean Yoon, Tae Hyung Park, Liang Fang, Kyung Min Kim, Cheol Seong Hwang:
A Stateful Logic Family Based on a New Logic Primitive Circuit Composed of Two Antiparallel Bipolar Memristors. Adv. Intell. Syst. 2(1): 1900082 (2020) - [j1]Binbin Yang, Nuo Xu, Cheng Li, Chenglong Huang, Desheng Ma, Jiahao Liu, Daniel Arumí, Liang Fang:
A forming-free ReRAM cell with low operating voltage. IEICE Electron. Express 17(22): 20200343 (2020)
Coauthor Index
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