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ORCIDVinay C. Patil
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2020 – today
- 2022
[j5]Vinay C. Patil
, Sandip Kundu:
Realizing Robust, Lightweight Strong PUFs for Securing Smart Grids. IEEE Trans. Consumer Electron. 68(1): 5-13 (2022)- [c20]D. Richard Kuhn, M. S. Raunak, Charles B. Prado, Vinay C. Patil, Raghu N. Kacker:
Combination Frequency Differencing for Identifying Design Weaknesses in Physical Unclonable Functions. ICST Workshops 2022: 110-117 - 2021
- [j4]Brunno F. Goldstein, Vinay C. Patil, Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe M. G. França, Sandip Kundu:
Preventing DNN Model IP Theft via Hardware Obfuscation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 267-277 (2021) - 2020
- [c19]Vinay C. Patil, Sandip Kundu:
On Leveraging Multi-threshold FinFETs for Design Obfuscation. ISVLSI 2020: 108-113
2010 – 2019
- 2019
- [j3]Leandro Santiago de Araújo, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu:
Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network. J. Hardw. Syst. Secur. 3(3): 235-249 (2019) - [c18]Leandro Santiago de Araújo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu:
Efficient Testing of Physically Unclonable Functions for Uniqueness. ATS 2019: 117-122 - [i1]Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu:
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques. CoRR abs/1910.00981 (2019) - 2018
- [j2]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 960-969 (2018) - [c17]Horacio L. França, Charles B. Prado, Vinay C. Patil, Sandip Kundu:
Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs. AsianHOST 2018: 25-30 - [c16]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
On IC traceability via blockchain. VLSI-DAT 2018: 1-4 - 2017
- [j1]Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu:
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques. IEEE Trans. Inf. Forensics Secur. 12(1): 64-77 (2017) - [c15]Leandro Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu:
Realizing strong PUF from weak PUF via neural computing. DFT 2017: 1-6 - [c14]Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu:
Improving reliability of weak PUFs via circuit techniques to enhance mismatch. HOST 2017: 146-150 - [c13]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF. ISCAS 2017: 1-4 - [c12]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
Determining proximal geolocation of IoT edge devices via covert channel. ISQED 2017: 196-202 - [c11]Pavithra Ramesh, Vinay C. Patil, Sandip Kundu:
Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment. NATW 2017: 1-4 - 2016
- [c10]Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
On meta-obfuscation of physical layouts to conceal design characteristics. DFT 2016: 147-152 - [c9]Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu:
Machine learning resistant strong PUF: Possible or a pipe dream? HOST 2016: 19-24 - [c8]Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
Preventing integrated circuit piracy via custom encoding of hardware instruction set. ISQED 2016: 234-241 - [c7]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On testing physically unclonable functions for uniqueness. ISQED 2016: 368-373 - [c6]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
An Efficient Method for Clock Skew Scheduling to Reduce Peak Current. VLSID 2016: 505-510 - 2014
- [c5]Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu:
On pattern generation for maximizing IR drop. ISQED 2014: 731-737 - [c4]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery. ISVLSI 2014: 510-515 - 2013
- [c3]Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu:
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. VLSI Design 2013: 80-85 - 2012
- [c2]Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators. ISVLSI 2012: 165-170 - 2011
- [c1]Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. ISVLSI 2011: 224-229
Coauthor Index
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