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ORCIDKamran Zarrineh
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2010 – 2019
- 2011
[c16]Salvatore Pontarelli, Marco Ottavi
, Adelio Salsano, Kamran Zarrineh:
Feedback based droop mitigation. DATE 2011: 879-882
2000 – 2009
- 2008
- [c15]Kamran Zarrineh:
Design for Test Challenges of High Performance/Low Power Microprocessors. DFT 2008: 503-503 - 2005
- [c14]Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara:
Design and analysis of multiple weight linear compactors of responses containing unknown values. ITC 2005: 10 - 2003
- [c13]Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod:
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. ITC 2003: 998-1007 - 2001
- [j2]Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane:
System-on-Chip Testability Using LSSD Scan Structures. IEEE Des. Test Comput. 18(3): 83-97 (2001) - [j1]Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty:
Automatic generation and compaction of March tests for memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 845-857 (2001) - [c12]Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams:
Defect Analysis and a New Fault Model for Multi-port SRAMs. DFT 2001: 366-374 - [c11]Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar:
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD 2001: 526-529 - 2000
- [c10]Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor:
Self test architecture for testing complex memory structures. ITC 2000: 547-556 - [c9]Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo:
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. MTDT 2000: 119-124
1990 – 1999
- 1999
- [c8]Kamran Zarrineh, Shambhu J. Upadhyaya:
On Programmable Memory Built-In Self Test Architectures. DATE 1999: 708-713 - [c7]Kamran Zarrineh, Shambhu J. Upadhyaya:
Programmable Memory BIST and a New Synthesis Framework. FTCS 1999: 352-355 - [c6]Kamran Zarrineh, Shambhu J. Upadhyaya:
A design for test perspective on memory synthesis. ISCAS (1) 1999: 101-104 - [c5]Kamran Zarrineh, Shambhu J. Upadhyaya:
A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units. VTS 1999: 391-397 - 1998
- [c4]Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty:
A new framework for generating optimal March tests for memory arrays. ITC 1998: 73-82 - [c3]Kamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III:
Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips. VTS 1998: 98-105 - 1997
- [c2]Vivek Chickermane, Kamran Zarrineh:
Addressing Early Design-For-Test Synthesis in a Production Environment. ITC 1997: 246-255 - 1996
- [c1]Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer:
A Design For Test Perspective on I/O Management. ICCD 1996: 46-53
Coauthor Index
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