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ORCIDJong-In Kim
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2010 – 2019
- 2019
[j4]Dong-Ryeol Oh
, Jong-In Kim, Dong-Shin Jo, Woo-Chul Kim, Dong-Jin Chang, Seung-Tak Ryu:
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. IEEE J. Solid State Circuits 54(1): 288-297 (2019)- 2018
- [c6]Yong-Jae Kim, Jong-In Kim, Wooseok Jang:
Quaternion Joint: Dexterous 3-DOF Joint Representing Quaternion Motion for High-Speed Safe Interaction. IROS 2018: 935-942 - 2017
- [j3]Jong-In Kim:
A two-step offset calibration in dynamic comparator using body voltage control. IEICE Electron. Express 14(21): 20170933 (2017) - [c5]Yong-Jae Kim, Yong-Jun Jeong, Hyeong-Seok Jeon, Deok-Won Lee, Jong-In Kim:
Development of a soft robotic glove with high gripping force using force distributing compliant structures. IROS 2017: 3883-3890 - [c4]Jong-In Kim, Hyeong-Seok Jeon, Yong-Jun Jeong, Yong-Jae Kim:
High stiffness capacitive type torque sensor with flexure structure for cooperative industrial robots. URAI 2017: 433-437 - 2015
- [j2]Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu:
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. IEEE J. Solid State Circuits 50(10): 2319-2330 (2015) - [c3]Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin-Gwang Kim, Seung-Tak Ryu:
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. ESSCIRC 2015: 323-326 - 2013
- [j1]Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim, Seung-Tak Ryu:
A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. IEEE J. Solid State Circuits 48(6): 1429-1441 (2013) - 2011
- [c2]Jong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu:
A time-domain latch interpolation technique for low power flash ADCs. CICC 2011: 1-4
2000 – 2009
- 2009
- [c1]Ba Sung, Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Kim, Seung-Tak Ryu:
A Time-interleaved Flash-SAR Architecture for High Speed A/D Conversion. ISCAS 2009: 984-987
Coauthor Index
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