default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDLiang-Chia Cheng
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2017
[j6]Chung-Han Chou
, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang:
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 146-155 (2017)- [c11]Hong-Wen Chiou, Yu-Min Lee, Hsuan-Hsuan Hsiao, Liang-Chia Cheng:
Thermal modeling and design on smartphones with heat pipe cooling technique. ICCAD 2017: 482-489 - 2016
- [j5]Hui Geng, Jianming Liu, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi:
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling. Integr. 55: 465-473 (2016) - [j4]Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi:
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1744-1754 (2016) - 2015
- [j3]Hui Geng, Jianming Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi:
Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 713-725 (2015) - 2014
- [j2]Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu:
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 947-951 (2014) - [c10]Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi:
Variation aware optimal threshold voltage computation for on-chip noise sensors. ICCAD 2014: 205-212 - [c9]Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng:
Incremental transient simulation of power grid. ISPD 2014: 93-100 - [c8]Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC 2014: 286-291 - 2013
- [c7]Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng:
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. Asian Test Symposium 2013: 107-108 - [c6]Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li:
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium 2013: 123-127 - [c5]Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi:
Benchmarking for research in power delivery networks of three-dimensional integrated circuits. ISPD 2013: 17-24 - [c4]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c3]Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng:
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. VLSI-DAT 2013: 1-4 - 2012
- [c2]Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi:
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. ASP-DAC 2012: 640-645 - [c1]Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi:
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs). ISVLSI 2012: 356-361
2000 – 2009
- 2008
- [j1]Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2097-2101 (2008)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:56 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
