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2010 – 2019
- 2011
[j9]Palanichamy Manikandan
, Bjørn B. Larsen, Einar J. Aas:
Design of embedded TCAM based longest prefix match search engine. Microprocess. Microsystems 35(8): 659-667 (2011)- [c25]Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
An Enhanced Path Delay Fault Simulator for Combinational Circuits. DSD 2011: 375-381 - [c24]Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef:
A programmable BIST with macro and micro codes for embedded SRAMs. EWDTS 2011: 144-150 - 2010
- [c23]Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
Path-Delay Fault Testing in Embedded Content Addressable Memories. DSD 2010: 519-524 - [c22]Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
Experiments with ABIST test methodology applied to path delay fault testing. EWDTS 2010: 59-63
2000 – 2009
- 2009
- [c21]Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system. ACM Great Lakes Symposium on VLSI 2009: 57-62 - 2008
- [j8]Sverre Wichlund, Frank Berntsen, Einar J. Aas:
Scan Test Response Compaction Combined with Diagnosis Capabilities. J. Electron. Test. 24(1-3): 235-246 (2008) - [j7]Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas:
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications. J. Signal Process. Syst. 53(3): 301-321 (2008) - 2007
- [c20]Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas:
Probabilistic gate-level power estimation using a novel waveform set method. ACM Great Lakes Symposium on VLSI 2007: 37-42 - 2006
- [c19]Sverre Wichlund, Einar J. Aas:
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor. ATS 2006: 421-430 - [c18]Sverre Wichlund, Frank Berntsen, Einar J. Aas:
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. DFT 2006: 119-127 - 2005
- [c17]Øystein Gjermundnes, Einar J. Aas:
Remote Path Delay Fault Simulation. DSD 2005: 428-434 - 2004
- [j6]Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Storage requirement estimation for optimized design of data intensive applications. ACM Trans. Design Autom. Electr. Syst. 9(2): 133-158 (2004) - 2003
- [j5]Øyvind Strøm, Kjetil Svarstad, Einar J. Aas:
On the Utilization of Java Technology in Embedded Systems. Des. Autom. Embed. Syst. 8(1): 87-106 (2003) - [j4]Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Data dependency size estimation for use in memory optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 908-921 (2003) - 2001
- [c16]Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. DAC 2001: 365-370 - [c15]Øyvind Strøm, Einar J. Aas:
An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. DSD 2001: 396-399 - [c14]Ayman M. Wahba, Einar J. Aas:
Formal verification of digital circuits by 3-valued simulation. ICECS 2001: 785-788 - 2000
- [c13]Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Storage requirement estimation for data intensive applications with partially fixed execution ordering. CODES 2000: 56-60 - [c12]Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. ICCAD 2000: 44-50 - [c11]Sverre Wichlund, Einar J. Aas:
On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning. ICECS 2000: 416-419 - [c10]Einar J. Aas:
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences. ISQED 2000: 389-394
1990 – 1999
- 1999
- [c9]Øyvind Strøm, Audun Klauseie, Einar J. Aas:
A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs. EUROMICRO 1999: 1232-1235 - [c8]Einar J. Aas, Jukka Typpo:
Project based learning objectives and experiences in electronic education: a memory controller design experiment. ICECS 1999: 1611-1614 - 1996
- [c7]Ingil Sundsbo, G. Lokken Hansen, Einar J. Aas:
Comparison of two architectures for implementation of the discrete cosine transform. ICASSP 1996: 3272-3275 - [c6]Johnny Pihl, Einar J. Aas:
4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit Technique. ISSPA 1996: 668-671 - 1994
- [j3]Einar J. Aas, Tore Steen, Karl Klingsheim:
Quantifying Design Quality Through Design Experiments. IEEE Des. Test Comput. 11(1): 27-38 (1994) - 1993
- [c5]Ayman M. Wahba, Einar J. Aas:
Verification and Diagnosis of Digital Systems by Termary Reasoning. CHARME 1993: 55-67 - 1991
- [j2]Bjørg Reppen, Einar J. Aas:
Combined probabilistic testability calculation and compact test generation for PLAs. J. Electron. Test. 2(3): 215-227 (1991) - [c4]Einar J. Aas, Gunnar Nystu:
Experiments with autonomous test of PLAs. EURO-DAC 1991: 503-509 - 1990
- [c3]Ove Brynestad, Einar J. Aas, Anne E. Vallestad:
State transition graph analysis as a key to BIST fault coverage. ITC 1990: 537-543
1980 – 1989
- 1984
- [j1]Dag Svanæs, Einar J. Aas:
Test generation through logic programming. Integr. 2(1): 49-67 (1984)
1970 – 1979
- 1978
- [c2]Hedayat Markus Bayegan, Einar J. Aas:
An integrated system for interactive editing of schematics, logic simulation and PCB layout design. DAC 1978: 1-8 - 1975
- [c1]P. A. Arneberg, Einar J. Aas:
Design automation in norway. DAC 1975: 251-256
Coauthor Index
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