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ORCIDWerner Grollitsch
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2020 – today
- 2023
[j4]Alessio Cortiula
, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 940-951 (2023)- 2020
- [j3]Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1369-1373 (2020) - [c11]Luigi Grimaldi, Dmytro Cherniak, Werner Grollitsch, Roberto Nonis:
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c10]Dylan D'Ampolo, Andrea Bandiziol, Davide Menin, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. APCCAS 2019: 225-228 - [c9]Alessio Cortiula, Martino Dazzi, Mattia Marcon, Davide Menin, Marco Scapol, Andrea Bandiziol, Andrea Cristofoli, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri:
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. MIPRO 2019: 112-116 - 2018
- [j2]Andrea Bandiziol, Werner Grollitsch, Giovanni Steffan, Roberto Nonis, Pierpaolo Palestri:
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1305-1309 (2018) - [c8]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri:
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. ISCAS 2018: 1-5 - 2016
- [c7]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. APCCAS 2016: 321-324 - [c6]Werner Grollitsch, Roberto Nonis:
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS. ESSCIRC 2016: 201-204 - [c5]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a transmitter for high-speed serial interfaces in automotive micro-controller. MIPRO 2016: 84-88 - 2015
- [c4]Andrea Cossettini, Andrea Cristofoli, Werner Grollitsch, Lino Alves, Roberto Nonis, Luca Della Ricca, Pierpaolo Palestri, Luca Selmi:
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall. RTSI 2015: 34-38 - 2013
- [j1]Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. IEEE J. Solid State Circuits 48(12): 3134-3145 (2013) - [c3]Nicola Da Dalt, Peter Pridnig, Werner Grollitsch:
An all-digital PLL using random modulation for SSC generation in 65nm CMOS. ISSCC 2013: 252-253 - [c2]Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. ISSCC 2013: 356-357 - 2010
- [c1]Werner Grollitsch, Roberto Nonis, Nicola Da Dalt:
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. ISSCC 2010: 478-479
Coauthor Index
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