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ORCIDDaniel Sánchez 0004
Person information
- affiliation: University of Murcia, Spain
Other persons with the same name
- Daniel Sánchez 0001
![[0000-0002-6048-3994]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-6048-3994")
— University of Granada, Department of Computer Science and Artificial Intelligence, Spain - Daniel Sánchez Morillo (aka: Daniel Sánchez 0002) — University of Cadiz, Biomedical Engineering and Telemedicine Research Group, Spain
- Daniel Sánchez 0003 — MIT CSAIL, Cambridge, MA, USA (and 1 more)
- Daniel Sánchez 0005 (aka: Daniel Sánchez Abril) — Universitat de Barcelona, Spain
- Daniel Sánchez 0006 — SRI International, Menlo Park, CA, USA
- Daniel Sánchez 0007 — Northwestern University, Evanston, IL, USA
- Daniel Sánchez 0008 — Florida International University, Miami, FL, USA
- Daniel Sánchez 0009 — Universidad de Valencia, Spain
- Daniel Sánchez 0010 — University of Puerto Rico
- Daniel Sánchez 0011 (aka: Daniel Sánchez Aranguren) — Osaka University, School of Engineering Science, Japan
- Daniel Sánchez 0012 — Universidad Distrital Francisco Jose de Caldas, Bogotá, Colombia
- Daniel Sánchez 0013 — Laboratorio de Circuitos y Sistemas Robustos (LCSR), Córdoba, Argentina
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Journal Articles
- 2015
[j5]Daniel Sánchez, Juan M. Cebrian, José M. García, Juan L. Aragón:
Soft-error mitigation by means of decoupled transactional memory threads. Distributed Comput. 28(2): 75-90 (2015)- 2014
- [j4]Juan M. Cebrian, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras:
Managing power constraints in a single-core scenario through power tokens. J. Supercomput. 68(1): 414-442 (2014) - 2013
- [j3]Juan M. Cebrian, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras:
Efficient inter-core power and thermal balancing for multicore processors. Computing 95(7): 537-566 (2013) - [j2]Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García, Juan L. Aragón:
Modeling the impact of permanent faults in caches. ACM Trans. Archit. Code Optim. 10(4): 29:1-29:23 (2013) - 2012
- [j1]Daniel Sánchez, Juan L. Aragón, José M. García:
A fault-tolerant architecture for parallel applications in tiled-CMPs. J. Supercomput. 61(3): 997-1023 (2012)
Conference and Workshop Papers
- 2011
- [c4]Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, José M. García:
An analytical model for the calculation of the Expected Miss Ratio in faulty caches. IOLTS 2011: 252-257 - 2010
- [c3]Daniel Sánchez, Juan L. Aragón, José M. García:
A log-based redundant architecture for reliable parallel computation. HiPC 2010: 1-10 - 2009
- [c2]Daniel Sánchez, Juan L. Aragón, José M. García:
REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. Euro-Par 2009: 321-333 - [c1]Daniel Sánchez, Juan L. Aragón, José M. García:
Extending SRT for parallel applications in tiled-CMP architectures. IPDPS 2009: 1-8
Coauthor Index
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