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ORCIDAndres J. Torres
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2020 – today
- 2024
[c8]J. Andres Torres:
Challenges and Opportunities in Heterogenous Integration During Design and Process Co-Optimization. MWSCAS 2024: 865-866- [c7]J. Andres Torres, Melody Tao, Anastasiia Doinychko, Mohan Govindaraj, Srividya Jayaram, Nathan Greeneltch:
Knowledge Transfer. From Electronic Design Automation to Advanced Process Manufacturing. MWSCAS 2024: 1329-1334 - 2020
- [j6]Dehia Ait-Ferhat, Vincent Juliard, Gautier Stauffer
, J. Andres Torres:
Combining lithography and Directed Self Assembly for the manufacturing of vias: Connections to graph coloring problems, integer programming formulations, and numerical experiments. Eur. J. Oper. Res. 280(2): 453-468 (2020) - [j5]Dehia Ait-Ferhat, Vincent Juliard, Gautier Stauffer, J. Andres Torres:
The k-path coloring problem in graphs of bounded treewidth: An application in integrated circuit manufacturing. Oper. Res. Lett. 48(5): 652-657 (2020)
2010 – 2019
- 2019
- [i2]Dehia Ait-Ferhat, Vincent Juliard, Gautier Stauffer, J. Andres Torres:
DSA-aware multiple patterning for the manufacturing of vias: Connections to graph coloring problems, IP formulations, and numerical experiments. CoRR abs/1902.04145 (2019) - [i1]Dehia Ait-Ferhat, Vincent Juliard, Gautier Stauffer, Andres J. Torres:
The $k$-path coloring problem in graphs with bounded treewidth: an application in integrated circuit manufacturing. CoRR abs/1904.11805 (2019) - 2017
- [c6]J. Andres Torres, Germain Fenger, Daman Khaira, Yuansheng Ma, Yuri Granik, Chris Kapral, Joydeep Mitra, Polina Krasnova, Dehia Ait-Ferhat:
Overview and development of EDA tools for integration of DSA into patterning solutions. ISQED 2017: 99-103 - 2016
- [c5]Fedor G. Pikus, Andres J. Torres:
Advanced multi-patterning and hybrid lithography techniques. ASP-DAC 2016: 611-616 - 2014
- [j4]Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis:
Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1170-1174 (2014) - 2013
- [j3]Lars Liebmann, J. Andres Torres:
A Designer's Guide to Subresolution Lithography: Enabling the Impossible to Get to the 14-nm Node [Tutorial]. IEEE Des. Test 30(3): 70-92 (2013) - [j2]Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis:
Litho-Friendly Decomposition Method for Self-Aligned Double Patterning. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1469-1480 (2013) - 2012
- [c4]J. Andres Torres:
ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite. ICCAD 2012: 349-350 - 2011
- [j1]Duo Ding, J. Andres Torres, David Z. Pan:
High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1621-1634 (2011) - [c3]Duo Ding, Andres J. Torres, Fedor G. Pikus, David Z. Pan:
High performance lithographic hotspot detection using hierarchically refined machine learning. ASP-DAC 2011: 775-780 - [c2]Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska:
Rapid layout pattern classification. ASP-DAC 2011: 781-786 - [c1]Minoo Mirsaeedi, J. Andres Torres, Mohab H. Anis:
Self-aligned double patterning (SADP) layout decomposition. ISQED 2011: 103-109
Coauthor Index
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