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ORCIDHassan A. Salamy
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2020 – today
- 2022
[j14]Dulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal:
Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis. Int. J. Parallel Emergent Distributed Syst. 37(6): 696-713 (2022)- 2021
- [j13]Dulana Rupanetti, Hassan A. Salamy:
Thermal and energy-aware utilisation management on MPSoC architectures. Int. J. Parallel Emergent Distributed Syst. 36(5): 449-469 (2021) - [c17]Matthew Ward, Kevin Malmsten, Hassan A. Salamy, Cheol-Hong Min:
Data Balanced Bagging Ensemble of Convolutional- LSTM Neural Networks for Time Series Data Classification with an Imbalanced Dataset. ISCAS 2021: 1-5 - [c16]Dulana Rupanetti, Hassan A. Salamy:
Energy-Aware Task Migration Through Ant-Colony Optimization for Multiprocessors. UEMCON 2021: 901-907 - 2020
- [j12]Hassan A. Salamy:
Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip. J. Circuits Syst. Comput. 29(9): 2050135:1-2050135:22 (2020) - [c15]Dulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min:
Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications. CCWC 2020: 228-233
2010 – 2019
- 2019
- [j11]Hassan A. Salamy:
An Effective Technique to Higher Throughput for Streaming Applications on an MPSoC. J. Comput. 14(8): 507-518 (2019) - [j10]Dulana Rupanetti, Hassan A. Salamy:
Task allocation, migration and scheduling for energy-efficient real-time multiprocessor architectures. J. Syst. Archit. 98: 17-26 (2019) - [c14]Dulana Rupanetti, Hassan A. Salamy:
Energy Efficient Scheduling with Task Migration on MPSoC Architectures. EIT 2019: 156-161 - [c13]Matthew Ward, Cheol-Hong Min, Hassan A. Salamy, Kundan Nepal:
Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition. ICECS 2019: 49-52 - [c12]Dulana Rupanetti, Hassan A. Salamy:
Thermal-Constrained. Energy-Aware Load Management on MPSoC Architectures. UEMCON 2019: 1168-1174 - 2017
- [j9]Hassan A. Salamy:
An effective approach to schedule time reduction on multi-core embedded systems. Comput. Electr. Eng. 64: 15-33 (2017) - [j8]Hassan A. Salamy, Semih Aslan:
Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC. J. Circuits Syst. Comput. 26(3): 1750042:1-1750042:22 (2017) - 2016
- [c11]Hassan A. Salamy, Mugdha Tasgaonkar:
Energy efficient scheduling for a stream of applications on an MPSoC under throughput constraints. EIT 2016: 659-664 - 2013
- [c10]Hassan A. Salamy, Semih Aslan, Divya Methukumalli:
Task scheduling on multicores under energy and power constraints. CCECE 2013: 1-4 - [c9]Hassan A. Salamy, Semih Aslan:
Energy-aware schedule optimization on multicore systems. MWSCAS 2013: 109-112 - [c8]Semih Aslan, Hassan A. Salamy, Jafar Saniie:
A high-level synthesis and verification tool for application specific kth Root Processing Engine. MWSCAS 2013: 1051-1054 - 2012
- [j7]Hassan A. Salamy:
Minimizing address arithmetic instructions in embedded applications on DSPs. Comput. Electr. Eng. 38(6): 1550-1563 (2012) - [j6]Hassan A. Salamy, J. Ramanujam
:
Code Size Reduction for Array Intensive Applications on Digital Signal Processors. J. Circuits Syst. Comput. 21(3) (2012) - [j5]Hassan A. Salamy, J. Ramanujam:
An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 717-725 (2012) - [j4]Hassan A. Salamy, J. Ramanujam:
Storage Optimization through Offset Assignment with Variable Coalescing. ACM Trans. Embed. Comput. Syst. 11(S1): 16 (2012) - [j3]Hassan A. Salamy, J. Ramanujam:
An ILP solution to address code generation for embedded applications on digital signal processors. ACM Trans. Design Autom. Electr. Syst. 17(3): 28:1-28:23 (2012) - [c7]Hassan A. Salamy, Haidar Harmanani:
An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates. MWSCAS 2012: 530-533 - 2011
- [c6]Hassan A. Salamy, Haidar M. Harmanani:
An optimal formulation for test scheduling network-on-chip using multiple clock rates. CCECE 2011: 215-218 - [c5]Hassan A. Salamy:
Compact code generation for embedded applications on digital signal processors. ICECS 2011: 563-566
2000 – 2009
- 2009
- [c4]Hassan A. Salamy, J. Ramanujam:
A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip. HiPEAC 2009: 263-277 - 2008
- [c3]Hassan A. Salamy, J. Ramanujam:
Optimal address register allocation for arrays in DSP applications. ESTIMedia 2008: 67-72 - [c2]Hassan A. Salamy, J. Ramanujam:
Storage optimization through code size reduction for digital signal processors. ESTIMedia 2008: 107-112 - 2006
- [j2]Haidar M. Harmanani, Hassan A. Salamy:
A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints. Int. J. Comput. Intell. Appl. 6(4): 511-530 (2006) - [j1]Haidar M. Harmanani, Hassan A. Salamy:
Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm. J. Circuits Syst. Comput. 15(3): 331-349 (2006) - [c1]Hassan A. Salamy, J. Ramanujam:
An Effective Heuristic for Simple Offset Assignment with Variable Coalescing. LCPC 2006: 158-172
Coauthor Index
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