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ORCIDGrzegorz Blakiewicz
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2020 – today
- 2023
[j11]Miron Klosowski
, Yichuang Sun, Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz, Stanislaw Szczepanski:
Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3258-3262 (2023)- 2020
- [j10]Grzegorz Blakiewicz, Jacek Jakusz, Miron Klosowski, Waldemar Jendernalik, Stanislaw Szczepanski:
Light-Powered Starter for Micro-Power Boost DC-DC Converter for CMOS Image Sensors. Circuits Syst. Signal Process. 39(3): 1195-1212 (2020) - [j9]Jacek Jakusz, Waldemar Jendernalik, Grzegorz Blakiewicz, Miron Klosowski, Stanislaw Szczepanski:
A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces. Sensors 20(11): 3303 (2020) - [j8]Grzegorz Blakiewicz, Miron Klosowski, Waldemar Jendernalik, Jacek Jakusz, Stanislaw Szczepanski:
Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2556-2565 (2020)
2010 – 2019
- 2018
- [j7]Miron Klosowski, Jacek Jakusz, Waldemar Jendernalik, Grzegorz Blakiewicz, Stanislaw Szczepanski, Slawomir Koziel:
A High-Efficient Measurement System With Optimization Feature for Prototype CMOS Image Sensors. IEEE Trans. Instrum. Meas. 67(10): 2363-2372 (2018) - 2017
- [j6]Miron Klosowski, Waldemar Jendernalik, Jacek Jakusz, Grzegorz Blakiewicz, Stanislaw Szczepanski:
A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 38-49 (2017) - 2015
- [j5]Tomasz Kulej, Grzegorz Blakiewicz:
A 0.5 V bulk-driven voltage follower/DC level shifter and its application in class AB output stage. Int. J. Circuit Theory Appl. 43(11): 1566-1580 (2015) - 2013
- [j4]Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz, Stanislaw Szczepanski, Robert Piotrowski:
An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 279-289 (2013) - 2011
- [j3]Grzegorz Blakiewicz:
Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower. IET Circuits Devices Syst. 5(5): 418-423 (2011) - [c7]Waldemar Jendernalik, Jacek Jakusz, Grzegorz Blakiewicz, Robert Piotrowski, Stanislaw Szczepanski:
Analog CMOS processor for early vision processing with highly reduced power consumption. ECCTD 2011: 745-748 - 2010
- [j2]Grzegorz Blakiewicz:
Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic. IET Circuits Devices Syst. 4(5): 458-467 (2010)
2000 – 2009
- 2008
- [c6]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Optimization of active circuits for substrate noise suppression. ISCAS 2008: 3418-3421 - 2007
- [j1]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Supply current spectrum estimation of digital cores at early design. IET Circuits Devices Syst. 1(3): 233-240 (2007) - 2006
- [c5]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Estimation of supply current spectrum for early noise evaluation. ISCAS 2006 - 2005
- [c4]Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang:
Substrate noise modeling in early floorplanning of MS-SOCs. ASP-DAC 2005: 819-823 - [c3]Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske:
Modeling of substrate noise block properties for early prediction. ISCAS (3) 2005: 3015-3018 - 2004
- [c2]Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang:
Substrate noise-aware floorplanning for mixed-signal SOCs. ISCAS (2) 2004: 445-448 - [c1]Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske:
Substrate noise optimization in early floorplanning for mixed signal SOCs. SoCC 2004: 301-304
Coauthor Index
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