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2010 – 2019
- 2012
[c2]Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott E. Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain:
A 32-core RISC microprocessor with network accelerators, power management and testability features. ISSCC 2012: 58-60
2000 – 2009
- 2006
- [c1]Vishnu Yalala, Derek Brasili, David Carlson, Adam Hughes, Anil Jain, Tim Kiszely, Kolar Kodandapani, Anand Varadharajan, Thucydides Xanthopoulos:
A 16-Core RISC Microprocessor with Network Extensions. ISSCC 2006: 305-314
1990 – 1999
- 1998
- [j1]Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen:
A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE J. Solid State Circuits 33(11): 1829-1839 (1998)
Coauthor Index
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