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ORCIDShinobu Miwa
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2020 – today
- 2024
[j16]Kohei Yoshida
, Shinobu Miwa, Hayato Yamaki, Hiroki Honda:
Analyzing the impact of CUDA versions on GPU applications. Parallel Comput. 120: 103081 (2024)- 2023
- [c28]Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda:
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. ASP-DAC 2023: 763-768 - [c27]Shinobu Miwa, Shin'ichiro Matsuo:
Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors. SC Workshops 2023: 1849-1858 - 2022
- [c26]Kohei Yoshida, Rio Sageyama, Shinobu Miwa, Hayato Yamaki, Hiroki Honda:
Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs. ICPP 2022: 65:1-65:12 - 2021
- [j15]Shinobu Miwa, Ignacio Laguna, Martin Schulz:
PredCom: A Predictive Approach to Collecting Approximated Communication Traces. IEEE Trans. Parallel Distributed Syst. 32(1): 45-58 (2021) - 2020
- [j14]Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda:
Evaluating architecture-level optimization in packet processing caches. Comput. Networks 181: 107550 (2020) - [j13]Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda:
RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache. IEICE Trans. Inf. Syst. 103-D(12): 2590-2599 (2020) - [j12]Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz:
Footprint-Based DIMM Hotplug. IEEE Trans. Computers 69(2): 172-184 (2020)
2010 – 2019
- 2019
- [c25]Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda:
Multi-Level Packet Processing Caches. COOL CHIPS 2019: 1-3 - [c24]Giorgis Georgakoudis, Nikhil Jain, Takatsugu Ono, Koji Inoue, Shinobu Miwa, Abhinav Bhatele:
Evaluating the Impact of Energy Efficient Networks on HPC Workloads. HiPC 2019: 301-310 - [c23]Yuta Inouchi, Hayato Yamaki, Shinobu Miwa, Tomoaki Tsumura:
Functionally-Predefined Kernel: a Way to Reduce CNN Computation. PACRIM 2019: 1-6 - 2018
- [c22]Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda:
Data prediction for response flows in packet processing cache. DAC 2018: 110:1-110:6 - 2016
- [j11]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. 99-D(12): 2881-2890 (2016) - [c21]Satoshi Shindo, Momoka Ohba, Tomoaki Tsumura, Shinobu Miwa:
Evaluation of Task Mapping on Multicore Neural Network Accelerators. CANDAR 2016: 415-421 - [c20]Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, Hiroki Honda:
Initial Study of Reconfigurable Neural Network Accelerators. CANDAR 2016: 707-709 - 2015
- [c19]Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura:
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD 2015: 149-156 - [c18]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD 2015: 455-458 - [c17]Shinobu Miwa, Hiroshi Nakamura:
Profile-based power shifting in interconnection networks with on/off links. SC 2015: 37:1-37:11 - 2014
- [j10]Shinobu Miwa, Takara Inoue, Hiroshi Nakamura:
Area-Efficient Microarchitecture for Reinforcement of Turbo Mode. IEICE Trans. Inf. Syst. 97-D(5): 1196-1210 (2014) - [j9]Shinobu Miwa, Sho Aita, Hiroshi Nakamura:
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology. Comput. Sci. Res. Dev. 29(3-4): 161-169 (2014) - [j8]Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9(4): 419-428 (2014) - [j7]Shinobu Miwa, Charles Lefurgy:
Evaluation of Core Hopping on POWER7. SIGMETRICS Perform. Evaluation Rev. 42(3): 55-60 (2014) - [c16]Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa:
Normally-off computing project: Challenges and opportunities. ASP-DAC 2014: 1-5 - [c15]Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu:
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA 2014: 1-6 - 2013
- [c14]Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
McRouter: Multicast within a router for high performance network-on-chips. PACT 2013: 319-329 - [c13]Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE 2013: 1813-1818 - [c12]Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. ICCD 2013: 349-356 - [c11]Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama:
Integrating Multi-GPU Execution in an OpenACC Compiler. ICPP 2013: 260-269 - [c10]Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops 2013: 842-850 - [c9]Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura:
Performance modeling for designing NoC-based multiprocessors. RSP 2013: 30-36 - 2012
- [j6]Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura:
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2301-2308 (2012) - [c8]Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura:
A novel power-gating scheme utilizing data retentiveness on caches. ACM Great Lakes Symposium on VLSI 2012: 91-94 - [c7]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI 2012: 233-238 - [c6]Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura:
Communication Library to Overlap Computation and Communication for OpenCL Application. IPDPS Workshops 2012: 567-573 - [c5]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED 2012: 625-632 - 2011
- [j5]Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo:
Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. IEICE Trans. Inf. Syst. 94-D(12): 2328-2337 (2011) - [j4]Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita:
A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth. J. Comput. Sci. Technol. 26(2): 292-301 (2011) - 2010
- [c4]Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo:
An Effective Replacement Policy Focusing on Lifetime of a Cache Line. CDES 2010: 146-152 - [c3]Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo:
Parallelizing Hilbert-Huang Transform on a GPU. ICNC 2010: 184-190
2000 – 2009
- 2009
- [j3]Jun Yao, Kosuke Ogata, Hajime Shimada, Shinobu Miwa, Hiroshi Nakashima, Shinji Tomita:
An Instruction Scheduler for Dynamic ALU Cascading Adoption. Inf. Media Technol. 4(4): 696-713 (2009) - [c2]Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo:
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES 2009: 171-177 - 2008
- [j2]Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita:
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases. IEICE Trans. Inf. Syst. 91-D(4): 1010-1022 (2008) - [c1]Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita:
Low-Complexity Bypass Network Using Small RAM. CDES 2008: 153-159 - 2007
- [j1]Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita:
Optimal pipeline depth with pipeline stage unification adoption. SIGARCH Comput. Archit. News 35(5): 3-9 (2007)
Coauthor Index
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