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ORCIDDATE 2013: Grenoble, France
- Enrico Macii:
Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. EDA Consortium San Jose, CA, USA / ACM DL 2013, ISBN 978-1-4503-2153-2
Keynotes
- Benedetto Vigna:
Smart systems for internet of things. 1 - Massoud Pedram:
Creating a sustainable information and communication infrastructure. 2
Acceleration and verification of ESL and analog systems
- Weiwei Chen, Rainer Dömer:
Optimized out-of-order parallel discrete event simulation using predictions. 3-8 - Matthieu Moy:
Parallel programming with SystemC for loosely timed models: a non-intrusive approach. 9-14 - David Novo, Sara El Alaoui, Paolo Ienne:
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. 15-20 - Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. 21-26 - Seyed-Hosein Attarzadeh-Niaki, Ingo Sander:
An automated parallel simulation flow for heterogeneous embedded systems. 27-30 - Peter Lisherness, Nicole Lesperance, Kwang-Ting (Tim) Cheng
:
Mutation analysis with coverage discounting. 31-34 - Hoang Minh Le, Daniel Große, Rolf Drechsler:
Scalable fault localization for SystemC TLM designs. 35-38
Energy optimization in multi-core systems
- Bharathwaj Raghunathan, Yatish Turakhia, Siddharth Garg, Diana Marculescu:
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors. 39-44 - Gang Chen, Kai Huang, Christian Buckl, Alois C. Knoll:
Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systems. 45-50 - Muhammad Shafique, Benjamin Vogel, Jörg Henkel:
Self-adaptive hybrid dynamic power management for many-core systems. 51-56 - Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li:
SmartCap: user experience-oriented power adaptation for smartphone's application processor. 57-60 - Dongwon Kim, Wonwoo Jung, Hojung Cha:
Runtime power estimation of mobile AMOLED displays. 61-64
Memory and cache architectures
- Seokin Hong, Soontae Kim:
AVICA: an access-time variation insensitive L1 cache architecture. 65-70 - Yen-Hao Chen, Yi-Yu Liu:
Dual-addressing memory architecture for two-dimensional memory access patterns. 71-76 - Fazal Hameed, Lars Bauer, Jörg Henkel:
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. 77-82 - Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato:
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. 83-88 - Michel El-Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie D. Enright Jerger, Andreas Moshovos:
A dual grain hit-miss detector for large die-stacked DRAM caches. 89-92 - Roberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado:
Reducing writes in phase-change memory environments by using efficient cache replacement policies. 93-96
Communications, multimedia, and consumer electronics
- Jochen Rust, Frank Ludwig, Steffen Paul:
Low complexity QR-decomposition architecture using the logarithmic number system. 97-102 - Wen Yueh, Minki Cho, Saibal Mukhopadhyay:
Perceptual quality preserving SRAM architecture for color motion pictures. 103-108 - Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel:
Parameterized area-efficient multi-standard turbo decoder. 109-114 - Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel:
An H.264 Quad-FullHD low-latency intra video encoder. 115-120 - Ziyuan Zhu, Shan Tang, Yongtao Su, Juan Han, Gang Sun, Jinglin Shi:
A 100 GOPS ASP based baseband processor for wireless communication. 121-124 - Muhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert, Jörg Henkel:
Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder. 125-128
Hot topic: reliability challenges of real-time systems in forthcoming technology nodes
- Said Hamdioui, Michael Nicolaidis, Dimitris Gizopoulos, Arnaud Grasset, Guido Groeseneken, Philippe Bonnot:
Reliability challenges of real-time systems in forthcoming technology nodes. 129-134
Safety critical real-time systems
- Moritz Neukirchner, Sophie Quinton, Tobias Michaels, Philip Axer, Rolf Ernst:
Sensitivity analysis for arbitrary activation patterns in real-time systems. 135-140 - Qingling Zhao, Zonghua Gu, Haibo Zeng:
PT-AMC: integrating preemption thresholds into mixed-criticality scheduling. 141-146 - Hang Su, Dakai Zhu:
An elastic mixed-criticality task model and its scheduling algorithm. 147-152 - Gonzalo Carvajal, Sebastian Fischmeister:
An open platform for mixed-criticality real-time ethernet. 153-156
Hot topic: IP subsystems: the next productivity wave?
- Pieter van der Wolf, Ruud Derwig:
Modular SoC integration with subsystems: the audio subsystem case. 157-162 - Pierre-Xavier Thomas, Grant Martin, David Heine, Dennis Moolenaar, James Kim:
Configurability in IP subystems: baseband examples. 163-168 - Frank Martin, Peter Bennett:
Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples. 169 - Menno Lindwer, Mark Ruvald Pedersen:
High-performance imaging subsystems and their integration in mobile devices. 170
Panel: the heritage of mead & conway: what has remained the same, what was missed, what has changed, what lies ahead
- Marco Casale-Rossi, Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Bernard Courtois, Hugo De Man, Antun Domic, Jan M. Rabaey:
Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead. 171-175
Addressing process and delay variation in high-level synthesis
- Mengying Zhao, Alex Orailoglu, Chun Jason Xue:
Profit maximization through process variation aware high level synthesis with speed binning. 176-181 - Yuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Instruction-set extension under process variation and aging effects. 182-187 - Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Multispeculative additive trees in high-level synthesis. 188-193 - Andrew Canis, Jason Helge Anderson, Stephen Dean Brown:
Multi-pumping for resource reduction in FPGA high-level synthesis. 194-197 - Yuankai Chen, Hai Zhou:
Resource-constrained high-level datapath optimization in ASIP design. 198-201
Microarchitectural techniques for reliability
- Yavuz Yetim, Margaret Martonosi, Sharad Malik:
Extracting useful computation from error-prone processors for streaming applications. 202-207 - Xing Hu, Guihai Yan, Yu Hu, Xiaowei Li:
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications. 208-213 - Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji:
Memory array protection: check on read or check on write? 214-219 - Gulay Yalcin, Osman S. Unsal, Adrián Cristal:
FaulTM: error detection and recovery using hardware transactional memory. 220-225 - Xavier Jimenez, David Novo, Paolo Ienne:
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. 226-229
Energy efficient mobile and cloud computing systems
- Roberto Diversi, Andrea Bartolini, Andrea Tilli, Francesco Beneventi, Luca Benini:
SCC thermal model identification via advanced bias-compensated least-squares. 230-235 - Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. 236-241 - William Lee, Vikas S. Vij, Anthony R. Thatcher, Kenneth S. Stevens:
Design of low energy, high performance synchronous and asynchronous 64-point FFT. 242-247 - Christian de Schryver, Pedro Torruella, Norbert Wehn:
A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model. 248-253 - Junyoung Park, Ameya Chaudhari, Jacob A. Abraham:
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor. 254-257 - Hao Shen, Qinru Qiu:
User-aware energy efficient streaming strategy for smartphone based video playback applications. 258-261 - Muhammad Abdullah Adnan, Rajesh Gupta:
Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity. 262-265 - Marina Zapater, José Luis Ayala, José Manuel Moya, Kalyan Vaidyanathan, Kenny C. Gross, Ayse K. Coskun:
Leakage and temperature aware server control for improving energy efficiency in data centers. 266-269
Dealing with timing variation in advanced technologies
- Fabian Oboril, Mehdi Baradaran Tahoori:
MTTF-balanced pipeline design. 270-275 - Marcus Wagner, Hans-Joachim Wunderlich:
Efficient variation-aware statistical dynamic timing analysis for delay test applications. 276-281 - Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta:
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology. 282-287 - Xiaolin Zhang, Jing Ye, Yu Hu, Xiaowei Li:
Capturing post-silicon variation by layout-aware path-delay testing. 288-291 - Chandra K. H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu:
Adaptive reduction of the frequency search space for multi-vdd digital circuits. 292-295
Timing analysis
- Nan Guan, Xinping Yang, Mingsong Lv, Wang Yi:
FIFO cache analysis for WCET estimation: a quantitative approach. 296-301 - Mircea Negrean, Sebastian Klawitter, Rolf Ernst:
Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems. 302-307 - Hardik Shah, Alois C. Knoll, Benny Akesson:
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis. 308-313
Hot topic: design for variability, manufacturability, reliability, and debug: many faces of the same coin?
- Rani S. Ghaida, Puneet Gupta:
Role of design in multiple patterning: technology development, design enablement and process control. 314-319 - David Lin, Ted Hong, Yanjing Li, Farzan Fallah, Donald S. Gardner, Nagib Hakim, Subhasish Mitra:
Overcoming post-silicon validation challenges through quick error detection (QED). 320-325 - Georges G. E. Gielen, Elie Maricau:
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS. 326-331
The quest for better NoCs
- Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick:
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems. 332-337 - Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, Li-Shiuan Peh:
SMART: a single-cycle reconfigurable NoC for SoC applications. 338-343 - Giorgos Dimitrakopoulos, N. Georgiadis, Chrysostomos Nicopoulos, Emmanouil Kalligeros:
Switch folding: network-on-chip routers with time-multiplexed output ports. 344-349 - Vahideh Akhlaghi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
An efficient network on-chip architecture based on isolating local and non-local communications. 350-353 - Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. 354-357
Embedded tutorial: reliability analysis reloaded: how will we survive?
- Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda:
Reliability analysis reloaded: how will we survive? 358-367
Emerging solutions to manage energy/performance trade-offs along the memory hierarchy
- Matthias Boettcher, Giacomo Gabrielli, Bashir M. Al-Hashimi, Danny Kershaw:
MALEC: a multiple access low energy cache. 368-373 - Chundong Wang, Weng-Fai Wong:
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems. 374-379 - Jie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen:
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. 380-385 - Jianhui Yue, Yifeng Zhu:
Exploiting subarrays inside a bank to improve phase change memory performance. 386-391 - Cedric Nugteren, Gert-Jan van den Braak, Henk Corporaal:
Future of GPGPU micro-architectural parameters. 392-395 - Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza:
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. 396-399 - Ali Jooya, Amirali Baniasadi:
Using synchronization stalls in power-aware accelerators. 400-403
Device identification and protection
- Nikolaus Theißing, Dominik Merli, Michael Smola, Frederic Stumpf, Georg Sigl:
Comprehensive analysis of software countermeasures against fault attacks. 404-409 - Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. 410-415 - Chi-En Daniel Yin, Gang Qu, Qiang Zhou:
Design and implementation of a group-based RO PUF. 416-421 - Yida Yao, MyungBo Kim, Jianmin Li, Igor L. Markov, Farinaz Koushanfar:
ClockPUF: physical unclonable functions based on clock networks. 422-427 - Patrick Koeberl, Ünal Koçabas, Ahmad-Reza Sadeghi:
Memristor PUFs: a new generation of memory-based physically unclonable functions. 428-431 - Álvaro Díaz Suárez, Pablo Sánchez Espeso, Juan Sancho, Juan Rico:
Wireless sensor network simulation for security and performance analysis. 432-435
New techniques for test pattern generation
- Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker:
Accurate QBF-based test pattern generation in presence of unknown values. 436-441 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Test solution for data retention faults in low-power SRAMs. 442-447 - Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker:
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. 448-453 - Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra:
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. 454-457
Hot topic: security challenges in automotive hardware/software architecture design
- Florian Sagstetter, Martin Lukasiewycz, Sebastian Steinhorst, Marko Wolf, Alexandre Bouard, William R. Harris, Somesh Jha, Thomas Peyrin, Axel Poschmann, Samarjit Chakraborty:
Security challenges in automotive hardware/software architecture design. 458-463
Hot topic - system approaches to energy-efficiency
- Nikola Rajovic, Alejandro Rico, James Vipond, Isaac Gelado, Nikola Puzovic, Alex Ramírez:
Experiences with mobile processors for energy efficient HPC. 464-468 - Xavier Vigouroux:
What designs for coming supercomputers? 469 - Wolfgang Lehner:
Energy-efficient in-memory database computing. 470-474 - Luka Stanisic, Brice Videau, Johan Cronsioe, Augustin Degomme, Vania Marangozova-Martin, Arnaud Legrand, Jean-François Méhaut:
Performance analysis of HPC applications on low-power embedded platforms. 475-480
Panel: can energy harvesting deliver enough power for automotive electronics?
- Robert Kappel, Günter Hofer, Gerald Holweg, Thomas Herndl:
Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting. 481 - Paul D. Mitcheson:
Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics? 482 - Christoph Grimm, Javier Moreno, Xiao Pan:
Ultra-low power: an EDA challenge. 483 - Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett:
DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters. 484
Post-silicon debug techniques
- Min Li, Azadeh Davoodi:
A hybrid approach for fast and accurate trace signal selection for post-silicon debug. 485-490 - Andrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco:
Machine learning-based anomaly detection for post-silicon bug diagnosis. 491-496 - Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda:
Space sensitive cache dumping for post-silicon validation. 497-502 - Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. 503-508 - Rohit Kumar Jain, Praveen Tiwari, Soumen Ghosh:
Automated determination of top level control signals. 509-512
Novel approaches for real-time architectures
- Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
A cache design for probabilistically analysable real-time systems. 513-518 - Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas:
MARTHA: architecture for control and emulation of power electronics and smart grid systems. 519-524 - Sven Goossens, Benny Akesson, Kees Goossens:
Conservative open-page policy for mixed time-criticality memory controllers. 525-530 - Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, Raphaël David:
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture. 531-534
Error-aware adaptive modern computing architectures
- Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi:
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. 535-540 - Abbas Rahimi, Andrea Marongiu, Paolo Burgio, Rajesh K. Gupta, Luca Benini:
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters. 541-546 - Zheng Wang, Kapil Singh, Chao Chen, Anupam Chattopadhyay:
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design. 547-552
Advances in mixed-signal, RF, and MEMS testing
- Ke Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris:
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests. 553-558 - Kai Hu, Bang-Ning Hsu, Andrew Madison, Krishnendu Chakrabarty, Richard B. Fair:
Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips. 559-564 - Ender Yilmaz, Geoff Shofner, LeRoy Winemberg, Sule Ozev:
Fault analysis and simulation of large scale industrial mixed-signal circuits. 565-570 - Lingfei Deng, Vinay Kundur, Naveen Sai Jangala Naga, Muhlis Kenan Ozel, Ender Yilmaz, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei, Divya Pratab, Tehmoor Dar:
Electrical calibration of spring-mass MEMS capacitive accelerometers. 571-574
Compilers and software synthesis for embedded systems
- Christophe Alias, Alain Darte, Alexandru Plesco:
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA. 575-580 - Reinhard von Hanxleden, Michael Mendler, Joaquín Aguado, Björn Duderstadt, Insa Fuhrmann, Christian Motika, Stephen Mercer, Owen O'Brien:
Sequentially constructive concurrency: a conservative extension of the synchronous model of computation. 581-586 - Zhonglei Wang, Jörg Henkel:
Fast and accurate cache modeling in source-level simulation of embedded software. 587-592 - Ke Bai, Aviral Shrivastava:
Automatic and efficient heap data management for limited local memory multicore architectures. 593-598 - Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng, Edwin Hsing-Mean Sha:
Software enabled wear-leveling for hybrid PCM main memory on embedded systems. 599-602 - Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger, Francisco J. Cazorla:
Probabilistic timing analysis on conventional cache designs. 603-606