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Yi-Hang Chen
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2010 – 2019
- 2017
- [c5]Juinn-Dar Huang
, Yi-Hang Chen, Jia-Shin Lu:
Defect-aware synthesis for reconfigurable single-electron transistor arrays. VLSI-SoC 2017: 1-6 - 2016
- [j1]Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
:
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints. ACM J. Emerg. Technol. Comput. Syst. 12(4): 37:1-37:15 (2016) - 2015
- [c4]Yi-Hang Chen, Yang Chen, Juinn-Dar Huang
:
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. VLSI-DAT 2015: 1-4 - 2014
- [c3]Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang:
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. DATE 2014: 1-4 - [c2]Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang
:
Two-staged parallel layer-aware partitioning for 3D designs. VLSI-DAT 2014: 1-4 - 2011
- [c1]Juinn-Dar Huang
, Yi-Hang Chen, Ya-Chien Ho:
Throughput optimization for latency-insensitive system with minimal queue insertion. ASP-DAC 2011: 585-590
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