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2010 – 2019
- 2014
[j8]Jen-Chieh Yeh, Chi-Hung Lin, Chun-Nan Liu:
Multi-core system performance prediction and analysis at the ESL. Int. J. Comput. Sci. Eng. 9(1/2): 86-94 (2014)- 2013
- [c10]Dung-Rung Hsieh, De-Jhen Huang, Jen-Yuan Hsu, Chieh-Yu Kao, Ming-Che Lin, Chun-Nan Liu, Pangan Ting:
Baseband design and software-defined-radio implementation for LTE femtocell. ASCC 2013: 1-6 - [c9]Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai:
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT 2013: 1-4 - 2012
- [c8]Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang:
Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement. HPCC-ICESS 2012: 1618-1623 - 2011
- [j7]Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei-Kuan Shih, An-Yeu Wu
:
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming. J. Signal Process. Syst. 62(3): 383-402 (2011) - [c7]Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh:
System-level design exploration for 3-D stacked memory architectures. CODES+ISSS 2011: 389-390 - [c6]Chao-Yi Cho, Tse-Min Chen, Wen-Shan Wang, Chun-Nan Liu:
Real-Time Photo Sensor Dead Pixel Detection for Embedded Devices. DICTA 2011: 164-169 - [c5]Yi-Ta Wu, Yih-Tyng Wu, Chao-Yi Cho, Shau-Yin Tseng, Chun-Nan Liu, Chung-Ta King:
Parallel Integral Image Generation Algorithm on Multi-core System. ISPA 2011: 31-35
2000 – 2009
- 2009
- [j6]Tsung-Han Tsai, Chun-Nan Liu:
Low-Power System Design for MPEG-2/4 AAC Audio Decoder Using Pure ASIC Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 144-155 (2009) - [c4]Tsung-Han Tsai, Chun-Nan Liu, Hsueh-Yi Lin, Hsing-Chuang Liu, Chia-Ying Wu:
A 1.4 MHz 0.21 mW MPEG-2/4 AAC single chip decoder. CICC 2009: 653-656 - 2008
- [j5]Tsung-Han Tsai, Chun-Nan Liu, Jui Hong Hung:
VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor. IEEE Trans. Consumer Electron. 54(2): 933-939 (2008) - [j4]Tsung-Han Tsai, Chun-Nan Liu:
A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards. J. Signal Process. Syst. 53(3): 323-333 (2008) - [c3]Chun-Nan Liu, Jui Hong Hung, Tsung-Han Tsai:
Optimization techniques of AAC decoder on PACDSP VLIW processor. ISCAS 2008: 1468-1471 - 2007
- [j3]Tsung-Han Tsai, Chun-Nan Liu:
A Configurable Common Filterbank Processor for Multi-Standard Audio Decoder. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(9): 1913-1923 (2007) - 2005
- [j2]Tsung-Han Tsai, Chun-Nan Liu:
A hardware/software co-design case study on MPEG AAC audio decoder. Int. J. Embed. Syst. 1(1/2): 125-133 (2005) - [j1]Tsung-Han Tsai, Ya-Chau Yang, Chun-Nan Liu:
A Hardware/Software Co-Design of MP3 Audio Decoder. J. VLSI Signal Process. 41(1): 111-127 (2005) - [c2]Chun-Nan Liu, Tsung-Han Tsai:
SoC platform based design of MPEG-2/4 AAC audio decoder. ISCAS (3) 2005: 2851-2854 - 2003
- [c1]Tsung-Han Tsai, Wen-Cheng Chen, Chun-Nan Liu:
A low power VLSI implementation for variable length decoder in MPEG-1 layer III. ICME 2003: 133-136
Coauthor Index
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