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Conference and Workshop Papers
- 2000
[c11]Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri
:
Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. IPDPS Workshops 2000: 924-931- [c10]Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri:
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. VLSI Design 2000: 212-219 - 1999
- [c9]Vinoo Srinivasan, Ranga Vemuri:
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. FCCM 1999: 272- - [c8]Vinoo Srinivasan, Ranga Vemuri:
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. FPGA 1999: 253 - [c7]Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, Jeffrey Walrath:
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops 1999: 588-596 - 1998
- [c6]Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri:
Hardware Software Partitioning with Integrated Hardware Design Space Exploration. DATE 1998: 28-35 - [c5]Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri:
An Effective Design System for Dynamically Reconfigurable Architectures. FCCM 1998: 312-313 - [c4]Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri:
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops 1998: 31-36 - [c3]Vinoo Srinivasan, Ranga Vemuri:
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. VLSI Design 1998: 435-441 - 1996
- [c2]Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri:
Rapid Prototyping of Reconfigurable Coprocessors. ASAP 1996: 303-312 - [c1]Vinoo Srinivasan, Nand Kumar, Ranga Vemuri:
Hierarchical behavioral partitioning for multicomponent synthesis. EURO-DAC 1996: 212-217
Coauthor Index
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