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Jack V. Briner Jr.

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1990 – 1999

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1994
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Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain:
Parallel Logic Simulation of VLSI Systems. ACM Comput. Surv. 26(3): 255-294 (1994)
1991
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Jack V. Briner Jr., John L. Ellis, Gershon Kedem:
Breaking the Barrier of Parallel Simulation of Digital Systems. DAC 1991: 223-226

1980 – 1989

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1988
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Jack V. Briner Jr.:
A Framework for Analyzing Parallel Discrete Event Simulation. Int. CMG Conference 1988: 180-185
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Jack V. Briner Jr., John L. Ellis, Gershon Kedem:
Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation. ICCAD 1988: 312-315

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