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2020 – today
- 2024
[j21]Pavia Bera, Stephen Cahoon, Sanjukta Bhanja, Alex K. Jones:
SPIMulator: A Spintronic Processing-in-memory Simulator for Racetracks. ACM Trans. Embed. Comput. Syst. 23(6): 94:1-94:27 (2024)- 2023
- [j20]Sébastien Ollivier
, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, Alex K. Jones:
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT. IEEE Trans. Computers 72(4): 1095-1109 (2023) - 2022
- [j19]Kawsher A. Roxy, Stephen Longofono, Sébastien Ollivier, Sanjukta Bhanja, Alex K. Jones:
Pinning Fault Mode Modeling for DWM Shifting. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3319-3323 (2022) - [c28]Sébastien Ollivier, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, Alex K. Jones:
CORUSCANT: Fast Efficient Processing-in-Racetrack Memories. MICRO 2022: 784-798 - [i5]Kawsher A. Roxy, Stephen Longofono, Sébastien Ollivier, Sanjukta Bhanja, Alex K. Jones:
Pinning Fault Mode Modeling for DWM Shifting. CoRR abs/2203.08303 (2022) - [i4]Prayash Dutta, Albert Lee, Kang L. Wang, Alex K. Jones, Sanjukta Bhanja:
A Multi-domain Magneto Tunnel Junction for Racetrack Nanowire Strips. CoRR abs/2205.12494 (2022) - 2021
- [i3]Sébastien Ollivier, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, Alex K. Jones:
PIRM: Processing In Racetrack Memories. CoRR abs/2108.01202 (2021) - [i2]Arifa Hoque, Alex K. Jones, Sanjukta Bhanja:
XDWM: A 2D Domain Wall Memory. CoRR abs/2112.12692 (2021) - 2020
- [j18]Ilia A. Bautista Adames, Sudeep Sarkar, Sanjukta Bhanja:
MatlabHTM: A sequence memory model of neocortical layers for anomaly detection. SoftwareX 11: 100491 (2020)
2010 – 2019
- 2019
- [c27]Sébastien Ollivier, Donald Kline Jr., Kawsher A. Roxy, Rami G. Melhem, Sanjukta Bhanja, Alex K. Jones:
Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories. DSN 2019: 375-387 - [c26]Sébastien Ollivier, Donald Kline Jr., Kawsher A. Roxy, Rami G. Melhem, Sanjukta Bhanja, Alex K. Jones:
The Power of Orthogonality. ISVLSI 2019: 100-102 - 2018
- [j17]Kawsher A. Roxy, Sanjukta Bhanja:
Non-Boolean Computing with Spintronic Devices. Found. Trends Electron. Des. Autom. 12(1): 1-123 (2018) - 2017
- [c25]Arifa Hoque, William Sutton, Kawsher A. Roxy, Sanjukta Bhanja:
Integrating emerging memory technologies into undergraduate logic design course: The impact of context based teaching. MSE 2017: 31-34 - [c24]Kawsher A. Roxy, Sanjukta Bhanja:
Variability tolerant reading of nanomagnetic energy minimizing co-processor. MWSCAS 2017: 413-416 - 2016
- [j16]Jayita Das, Kevin Scott, Sanjukta Bhanja:
MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells. ACM J. Emerg. Technol. Comput. Syst. 13(1): 2:1-2:15 (2016) - [c23]Ilia A. Bautista Adames, Jayita Das, Sanjukta Bhanja:
Survey of Emerging Technology Based Physical Unclonable Funtions. ACM Great Lakes Symposium on VLSI 2016: 317-322 - 2015
- [j15]Aida Todri-Sanial, Sanjukta Bhanja:
Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies. ACM J. Emerg. Technol. Comput. Syst. 12(2): 11:1-11:2 (2015) - 2014
- [j14]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Nano Magnetic STT-Logic Partitioning for Optimum Performance. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 90-98 (2014) - [p1]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
STT-Based Non-Volatile Logic-in-Memory Framework. Field-Coupled Nanocomputing 2014: 173-193 - [e3]Neal G. Anderson, Sanjukta Bhanja:
Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives. Lecture Notes in Computer Science 8280, Springer 2014, ISBN 978-3-662-43721-6 [contents] - 2012
- [j13]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 2008-2016 (2012) - [c22]Sneta Mishra, Sanjukta Bhanja:
Evaluation of circuit styles and VLSI logic designs of pentacene OTFTs. MWSCAS 2012: 121-124 - [c21]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Non-destructive variability tolerant differential read for non-volatile logic. MWSCAS 2012: 178-181 - 2011
- [j12]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 267-276 (2011) - [j11]Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja:
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectron. Reliab. 51(2): 485-501 (2011) - [j10]Anita Kumari, Sanjukta Bhanja:
Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 714-717 (2011) - [c20]Sanjukta Bhanja, Javier F. Pulecio:
A review of magnetic cellular automata systems. ISCAS 2011: 2373-2376 - [c19]Saket Srivastava, Arjun Asthana, Sanjukta Bhanja, Sudeep Sarkar:
QCAPro - An error-power estimation tool for QCA circuit design. ISCAS 2011: 2377-2380 - [c18]D. K. Karunaratne, Srinath Rajaram, Kristin Kusmierek, Paromita De, Sanjukta Bhanja:
Novel knowledge module on fusion of logic and memory to undergraduate students. MSE 2011: 64-67
2000 – 2009
- 2009
- [j9]Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja:
Probabilistic Error Modeling for Nano-Domain Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 55-65 (2009) - [c17]Anita Kumari, Javier F. Pulecio, Sanjukta Bhanja:
Defect characterization in magnetic field coupled arrays. ISQED 2009: 436-441 - [c16]Anita Kumari, Sanjukta Bhanja:
CNT logic knowledge module integrated in digital CMOS logic design course. MSE 2009: 115-117 - [c15]Karthikeyan Lingasubramanian, Sanjukta Bhanja:
An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. VLSI Design 2009: 485-490 - [e2]Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar:
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. ACM 2009, ISBN 978-1-60558-522-2 [contents] - [i1]Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja:
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis. CoRR abs/0906.3282 (2009) - 2008
- [j8]Saket Srivastava, Sanjukta Bhanja:
Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course. IEEE Trans. Educ. 51(3): 349-355 (2008) - [j7]Sanjukta Bhanja, Sudeep Sarkar:
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 528-541 (2008) - [e1]Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja:
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008. ACM 2008, ISBN 978-1-59593-999-9 [contents] - 2007
- [j6]Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli:
QCA Circuits for Robust Coplanar Crossing. J. Electron. Test. 23(2-3): 193-210 (2007) - [j5]Saket Srivastava, Sanjukta Bhanja:
Hierarchical Probabilistic Macromodeling for QCA Circuits. IEEE Trans. Computers 56(2): 174-190 (2007) - [c14]Karthikeyan Lingasubramanian, Sanjukta Bhanja:
Probabilistic maximum error modeling for unreliable logic circuits. ACM Great Lakes Symposium on VLSI 2007: 223-226 - [c13]Saket Srivastava, Sanjukta Bhanja:
Integrating Nano-logic into an Undergraduate Logic Design Course. MSE 2007: 55-56 - 2006
- [j4]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006) - [j3]Thara Rejimon, Sanjukta Bhanja:
A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1130-1139 (2006) - [c12]Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli:
Novel designs for thermally robust coplanar crossing in QCA. DATE 2006: 786-791 - [c11]Thara Rejimon, Sanjukta Bhanja:
Wide Limited Switch Dynamic Logic Circuit Implementations. VLSI Design 2006: 94-99 - 2005
- [c10]Nirmal Ramalingam, Sanjukta Bhanja:
Causal probabilistic input dependency learning for switching model in VLSI circuits. ACM Great Lakes Symposium on VLSI 2005: 112-115 - [c9]Vijay K. Jain, Sanjukta Bhanja, Glenn H. Chapman, Lavanya Doddannagari, Nguyen Nguyen:
A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor. ICASSP (5) 2005: 77-80 - [c8]Vijay K. Jain, Sanjukta Bhanja, Glenn H. Chapman, Lavanya Doddannagari:
A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC. SoCC 2005: 243-246 - [c7]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591 - [c6]Thara Rejimon, Sanjukta Bhanja:
An Accurate Probalistic Model for Error Detection. VLSI Design 2005: 717-722 - 2004
- [j2]Sanjukta Bhanja, N. Ranganathan:
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1360-1370 (2004) - [c5]Shiva Shankar Ramani, Sanjukta Bhanja:
Any-time probabilistic switching model using bayesian networks. ISLPED 2004: 86-89 - 2003
- [j1]Sanjukta Bhanja, N. Ranganathan:
Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 558-567 (2003) - 2002
- [c4]Sanjukta Bhanja, N. Ranganathan:
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD 2002: 388-390 - [c3]Sanjukta Bhanja, N. Ranganathan:
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. ASP-DAC/VLSI Design 2002: 187-192 - 2001
- [c2]Sanjukta Bhanja, N. Ranganathan:
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC 2001: 209-214
1990 – 1999
- 1998
- [c1]Sanjukta Bhanja, Lynn M. Fletcher-Heath, Lawrence O. Hall, Dmitry B. Goldgof, Jeffrey P. Krischer:
A Qualitative Expert System for Clinical Trial Assignment. FLAIRS 1998: 84-88
Coauthor Index
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last updated on 2024-10-31 20:17 CET by the dblp team
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