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"24-bit significand multiplier for FPGA floating-point multiplication."

E. George Walters III (2015)

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DOI: 10.1109/ACSSC.2015.7421227

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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E. George Walters III:
24-bit significand multiplier for FPGA floating-point multiplication. ACSSC 2015: 717-721

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