"Deeply scaled VLSI analog transistor design and optimization."

Peng Lu et al. (2017)

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DOI: 10.1109/ASICON.2017.8252662

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-17

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Peng Lu, Po-Yen Chien, Xicheng Duan, Jason C. S. Woo:
Deeply scaled VLSI analog transistor design and optimization. ASICON 2017: 1061-1064

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