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"A low-power and high-efficiency cache design for embedded bus-based ..."

Xiantuo Rao et al. (2013)

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DOI: 10.1109/ASICON.2013.6811823

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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Xiantuo Rao, Teng Wang, Xin'an Wang, Yinhui Wang:
A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors. ASICON 2013: 1-4

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