"A high-resolution pipeline time-to-digital converter in 0.18μm CMOS ..."

Yongsheng Wang et al. (2017)

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DOI: 10.1109/ASICON.2017.8252553

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-17

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Yongsheng Wang, Qiao Ye, Han Zhao, Xiaowei Liu:
A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology. ASICON 2017: 624-627

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