"A mixed-signal simulator for VHDL-AMS."

Liyi Xiao et al. (2001)

> Home

Details and statistics

DOI: 10.1145/370155.370352

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/aspdac/LiyiBYGJP01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/LiyiBYGJP01
Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang:
A mixed-signal simulator for VHDL-AMS. ASP-DAC 2001: 287-292

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.