"Physical-Aware Memory BIST Datapath Synthesis: Architecture and ..."

V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra (2011)

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DOI: 10.1109/ATS.2011.102

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type: Conference or Workshop Paper

metadata version: 2023-03-24

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V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra:
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. Asian Test Symposium 2011: 457-458

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