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"Physical-Aware Memory BIST Datapath Synthesis: Architecture and ..."
V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra (2011)
- V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra:
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. Asian Test Symposium 2011: 457-458
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