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"Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features."

Amitava Majumdar, Balakrishna Jayadev (2018)

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DOI: 10.1109/ATS.2018.00018

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-18

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/ats/MajumdarJ18
Amitava Majumdar, Balakrishna Jayadev:
Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. ATS 2018: 36-41

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