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"Localized Verification of Circuit Descriptions."

Jørgen Staunstrup, Stephen J. Garland, John V. Guttag (1989)

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DOI: 10.1007/3-540-52148-8_29

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-19

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  - conf/avmfss/StaunstrupGG89
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  - https://dblp.org/rec/conf/avmfss/StaunstrupGG89
Jørgen Staunstrup, Stephen J. Garland, John V. Guttag:
Localized Verification of Circuit Descriptions. Automatic Verification Methods for Finite State Systems 1989: 349-364

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