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"A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA ..."
Thibaut Stimpfling et al. (2018)
- Thibaut Stimpfling, J. M. Pierre Langlois, Normand Bélanger, Yvon Savaria:

A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. CCGrid 2018: 402-411

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