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"Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL ..."

David E. Duarte et al. (2010)

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DOI: 10.1109/CICC.2010.5617473

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor:
Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. CICC 2010: 1-4

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