"An energy efficient 32nm 20 MB L3 cache for Intel® ..."

Min Huang et al. (2012)

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DOI: 10.1109/CICC.2012.6330624

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Min Huang, Moty Mehalel, Ramesh Arvapalli, Songnian He:
An energy efficient 32nm 20 MB L3 cache for Intel^® Xeon^® processor E5 family. CICC 2012: 1-4

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