"A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns."

Mark Jacunski et al. (2010)

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DOI: 10.1109/CICC.2010.5617634

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-25

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Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. CICC 2010: 1-4

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