"Design guideline for resistive termination of on-chip high-speed ..."

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera (2005)

> Home

Details and statistics

DOI: 10.1109/CICC.2005.1568742

access: closed

type: Conference or Workshop Paper

metadata version: 2022-01-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/TsuchiyaHO05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/TsuchiyaHO05
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Design guideline for resistive termination of on-chip high-speed interconnects. CICC 2005: 613-616

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.