"Cost-Effective Computational Modeling of Fault Tolerant Optimization of ..."

H. Girish, D. R. Shashikumar (2017)

> Home

Details and statistics

DOI: 10.1007/978-3-319-57264-2_1

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/csoc/GirishS17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/csoc/GirishS17
H. Girish, D. R. Shashikumar:
Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM Cells. CSOC (2) 2017: 1-12

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.