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"Efficient transistor-level timing yield estimation via line sampling."

Hiromitsu Awano, Takashi Sato (2016)

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DOI: 10.1145/2897937.2898016

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-17

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Hiromitsu Awano, Takashi Sato:
Efficient transistor-level timing yield estimation via line sampling. DAC 2016: 115:1-115:6

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