Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FPGA area reduction by multi-output function based sequential resynthesis."

Yu Hu et al. (2008)

> Home

Details and statistics

DOI: 10.1145/1391469.1391478

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dac/HuSMH08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/HuSMH08
Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
FPGA area reduction by multi-output function based sequential resynthesis. DAC 2008: 24-29

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.