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"A high-level synthesis flow for the implementation of iterative stencil ..."
Alessandro Antonio Nacci et al. (2013)
- Alessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza:
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. DAC 2013: 52:1-52:6
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