"Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip."

Heikki Kariniemi, Jari Nurmi (2006)

> Home

Details and statistics

DOI: 10.1109/DDECS.2006.1649609

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/ddecs/KariniemiN06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ddecs/KariniemiN06
Heikki Kariniemi, Jari Nurmi:
Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip. DDECS 2006: 186-191

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.